Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

3.3.3. Reset Scheme

The reset signals of the design example—master_reset_n and channel_reset_n[n:0]—are asynchronous and active-low signals. Asserting the master_reset_n signal resets all channels and their components; asserting the channel_reset_n[n] signal resets only the n channel and its components.

Upon power-up, reset the example design by asserting the master_reset_n signal. The following diagram shows the master reset scheme for the design example.

Figure 21. Master Reset

The following diagram shows the channel reset scheme for the design example. The mm_reset signal is used to reset the registers of the design components, whereas the datapath_reset is used to reset all digital blocks including the transceiver reset controller. The mm_reset and datapath_reset are triggered at the same time because they are tied together.

The reset csr block triggers the MAC reset only when the PHY's speed changes, which is indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link is lost, you can set the parameter PHY2MAC_RESET_EN to 1 in altera_eth_channel_1588.v/altera_eth_channel.sv

Figure 22. Channel Reset

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