Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

6.3.5. Timing Constraints

When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intel® recommends that you refer to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core section of Intel® Arria® 10 Transceiver PHY User Guide for details on the timing constraint examples.

In addition, you must set the false path from 10G PHY clock to Low Latency (LL) Ethernet 10G (10GbE) MAC logic and vice versa. Since the LL 10GbE MAC logic is not running 10G PHY clock, you do not need to ensure timing closure for LL 10GbE MAC data path at 10G PHY clock. For example:
set_false_path -from [get_clocks "$rx_pma_clk_10g_name $rx_clkout_10g_name $tx_pma_clk_10g_name $tx_clkout_10g_name"] -to [get_registers *|alt_em10g32:*|*]
set_false_path -from [get_registers *|alt_em10g32:*|*] -to [get_clocks "$rx_pma_clk_10g_name $rx_clkout_10g_name $tx_pma_clk_10g_name $tx_clkout_10g_name"]
where the path indicated by rx_pma_clk_10g_name, rx_clkout_10g_name, tx_clkout_10g_name, and tx_clkout_10g_name is associated with the 10G PHY clock, whereas the alt_em10g32 path indicates the LL 10GbE MAC logic.