Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

4.1. Features

  • Supports single Ethernet channels operating at 10G using Intel® Arria® 10 Native PHY.
  • Option to generate the design example with the 10GBASE-R register mode enabled.
  • 140 ns round-trip latency in simulation when the register mode is enabled.
  • Packet monitoring on the TX and RX datapaths.
  • Tested with the Spirent TestCenter.