Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

3.6. Interface Signals

Figure 27. Interface Signals of the 1G/10G Ethernet Design Example
Table 15.  Clock Domains
Clock Frequency (MHz) Interface Signals
xgmii_clk 156.25
  • Avalon® streaming interface
  • Packet Classifier interface
  • IEEE 1588v2 time-stamp interface
  • channel_ready[n] (PHY interface)
mm_clk 125
  • Avalon® memory-mapped interface
pll_ref_clk_1g 125
  • master_pulse_per_second (TOD interface)