Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683063
Date 1/11/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices 3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices 4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices 5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices 6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices 8. Interface Signals Description 9. Configuration Registers Description 10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives 11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the Design in Hardware
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Compiling and Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Testing the Design in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.4. Simulation x
2.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 2.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
2.5. Hardware Testing x
2.5.1. Test Cases 2.5.2. Signal Tap Debug Signals
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Cases 3.5.2. Signal Tap Debug Signals
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking and Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Cases 4.5.2. Signal Tap Debug Signals
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signal 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme 5.3.4. Partial Reconfiguration Ready
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 5.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme 6.3.4. Partial Reconfiguration Ready 6.3.5. Timing Constraints
6.5. Hardware Testing x
6.5.1. Test Procedure
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.4. Simulation x
7.4.1. Test Case
7.5. Hardware Testing x
7.5.1. Test Procedure
8. Interface Signals Description x
8.1. Clock and Reset Interface Signals 8.2. Avalon® Memory-Mapped Interface Signals 8.3. Avalon® Streaming Interface Signals 8.4. PHY Interface Signals 8.5. Status Interface 8.6. IEEE 1588v2 Timestamp Interface Signals 8.7. Packet Classifier Interface Signals 8.8. ToD Interface Signals
9. Configuration Registers Description x
9.1. Register Access Definition 9.2. Low Latency Ethernet 10G MAC 9.3. PHY 9.4. Transceiver Reconfiguration 9.5. TOD
9.3. PHY x
9.3.1. 1G/10G PHY 9.3.2. 1G/2.5G/5G/10G Multi-rate PHY
1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.01.11 19.1 19.1 Updated the following figures;
  • Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature in 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices topic.
  • Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature in 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices topic.
  • Clocking Scheme for the 1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature in 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices topic.
  • Clocking Scheme for the 1G/2.5G/10G Ethernet Design Example in 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices topic.
2020.11.30 19.1 19.1
  • Updated Table: 1G/2.5G/5G/10G Multi-rate Register Definitions.
  • Updated the following figures:
    • Clocking and Reset Scheme for 10GBASE-R Design Example
    • Clocking and Reset Scheme for 10GBASE-R Design Example with the Register Mode Enabled
    • Interface Signals of the 10GBASE-R Ethernet Design Example.
  • Updated Table: Clock of Reset Interface Signals:
    • Removed the rx_xcvr_half_clk signal.
    • Updated the tx_xcvr_half_clk signal name to iopll_half_clk signal.
  • Updated for latest branding standards.
2019.09.23 19.1 19.1
  • Added a note in the following topic to state that the Xcelium* simulator is supported in Intel® Quartus® Prime Pro Edition software only:
    • Directory Structure
    • Procedure in Compiling and Simulating the Design
  • Updated the Hardware and Software Requirements topics for all design example chapters.
2019.05.10 19.1 19.1
  • Updated Table: Parameters in the Example Design Tab:
    • Updated the parameter name Example Design Files for Simulation or Synthesis to Example Design Files.
    • Updated the parameter name Enable NPDME support to Enable Native PHY Debug Master Endpoint (NPDME).
  • Updated Figure: Example Design Tab.
2019.04.15 19.1 19.1
  • Changed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
2018.10.05 18.0 18.0
  • Updated Figure: Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example.
  • Updated Table: Avalon-MM Interface Signals:
    • Added the following signals: csr_mch_write, csr_mch_writedata, csr_mch_read, csr_mch_readdata, csr_mch_address, and csr_mch_waitrequest.
    • Removed the following signals: csr_write, csr_writedata, csr_read, csr_readdata, csr_address, and csr_waitrequest
  • Updated Table: Parameters in the Example Design Tab:
    • Added a note to parameter Enable ADME support to clarify that this option is only available from Intel Quartus Prime Pro Edition version 17.0 onwards.
    • Added a note to parameter Partial Reconfiguration Ready to clarify that this option is only available from Intel Quartus Prime Pro Edition version 17.1 onwards.
  • Updated the Configuration Registers Description chapter:
    • Added the Register Access Definition topic.
    • Added the following PHY topics:
      • 1G/10G PHY
      • 1G/2.5G/5G/10G PHY
  • Added Timing Constraint topic to 1G/2.5G/10G Ethernet Design Example for Intel Arria 10 Devices chapter.
2018.05.16 18.0 18.0
  • Renamed the document as Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide.
  • Updated the 10G USXGMII Ethernet Design Example for Intel Arria 10 Devices chapter:
    • Added 10M/100M speed support for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example.
    • Updated all references to 10G USXGMII references to 10M/100M/1G/2.5G/5G/10G (USXGMII).
    • Updated Table: Command Parameters.
    • Updated Table: Register Map to include byte offset for Native PHY Reconfiguration block.
  • Added support for Xcelium simulator.
  • Updated the procedure steps of the Compiling and Testing the Design in Hardware topic.
  • Restructured description for Hardware Testing topics for all design example chapters.
  • Updated Table: Clock and Reset Interface Signals.
  • Updated the following Figures:
    • Directory Structure for the Design Example
    • Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature
    • Master Reset
    • Interface Signals of the 10GBASE-R Ethernet Design Example
    • Master Reset for 10M/100M/1G/10G and 1G/10G Ethernet design examples.
  • Updated for latest branding standards.
  • Made editorial updates throughout the document.
2018.03.28 17.1 17.1
  • Updated 10G USXGMII Ethernet Design Example section:
    • Corrected Y5 value from 322.265625 MHz to 644.53125 Mhz in the Hardware Testing topic.
    • Updated Figure: Clocking Scheme for 10G USXGMII Ethernet Design Example.
    • Added a step on Test Procedure topic to enable PHY serial loopback on Channel 0.
Date Version Changes
November 2017 2017.11.13
  • Updated Figure: Example Design Tab.
  • Updated the Clocking and Reset scheme for 10GBASE-R Design example: Added tx_coreclkin and rx_coreclkin clock ports to the PHY block.
2017.11.06
  • Renamed the document as Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Arria 10 Devices.
  • Updated the descriptions for FIFO component in the "Design Components" table for the 10M/100M/1G/ 10G, 1G/10G, 10BASE-R, 1G/2.5G, 1G/2.5G/10G, and 10G USXGMII Ethernet design examples.
  • Added notes to clarify that the IOPLL input reference clock is sourcing from input clock through global clock network in the Clocking Schemes topics for the 10M/100M/1G/ 10G, 1G/10G, and 10GBASE-R Ethernet design examples.
  • Updated the Quick Start Guide section:
    • Updated Figures: Example Design Tab and Block Diagram of the Hardware Setup
    • Updated the "Directory and File Description" table.
    • Removed rtl directory from the "Directory and File Description" table.
    • Changed heading title of the Design Parameters Description topic to Design Example Parameters.
    • Changed heading title of the Design Parameters Description topic to Design Example Parameters.
    • Updated the "Parameters in the Example Design Tab" table:
      • Added Enable ADME support parameter and description.
      • Updated the descriptions for Generate File Format and Select Board parameters.
    • Updated the Procedure subtopic under Compiling and Simulating the Design topic.
  • Updated the 10M/100M/1G/10G Ethernet Design Example chapter:
    • Renamed the topic Multi-speed 10M – 10G Ethernet Design Examples to 10M/100M/1G/10G Ethernet Design Example.
  • Updated the 10BASE-R Ethernet Design Example chapter:
    • Renamed the topic 10BASE-R Design Examples to 10BASE-R Ethernet Design Examples.
    • Updated Figure: Block Diagram—10GBASE-R Design Example
    • Updated csr_clk value from 100 MHz to 125 MHz in the "Clocking and Reset Scheme for 10GBASE-R Design Example" figure.
    • Updated "Register Map" table: Updated the byte offset values for RX SC FIFO and TX SC FIFO.
    • Updated the description in the Hardware Description topic.
  • Updated 1G/2.5G Ethernet Design Example chapter:
    • Updated the 1G/2.5G Ethernet Design Example topic.
    • Added Topic—Partial Reconfiguration Ready.
  • Updated the 1G/2.5G/10G Ethernet Design Example chapter:
    • Updated the 1G/2.5G/10G Ethernet Design Example topic.
    • Added Topic—Partial Reconfiguration Ready.
    • Added Figure—Sample Simulation Output
  • Updated 10G USXGMII Ethernet Design Examples chapter:
    • Updated the 10G USXGMII Ethernet Design Example topic.
    • Updated "Design Components" table: Added channel address decoder, multi-channel address decoder, and top address decoder components.
    • Updated the description in the Hardware Description topic.
    • Added Figure—Sample Simulation Output
    • Updated "Clocking Scheme for 10G USXGMII Ethernet Design Example" and "Reset Scheme for 10G USXGMII Ethernet Design Example" figures: Updated the reference clock value from 644.53125 MHz to 322.265625 MHz.
  • Updated "Clock and Reset Interface Signals table: Updated the description for the mm_clk and csr_clk signals.
  • Updated PHY topic:
    • Updated "PMA Registers" table: Updated bit values of five registers.
    • Updated "Intel Arria 10 GMII PCS Registers" table: Updated bit names for 0x1240.
  • Merged the 10G TOD, and 1G TOD topics with the Master TOD and changed heading title to ToD.
  • Updated "ToD Register Map" table: Added bits information.
  • Updated for latest branding standards.
  • Made editorial updates throughout the document.
June 2017 2017.06.20 Corrected typographical errors in the Design Components topic for 1G/2.5G Ethernet design example.
2017.06.19
  • Rebranded as Intel.
  • Updated the "Transceiver Reconfiguration Register Map" table to include operation speed support of 10 Gbps for control register.
  • Added Partial Reconfiguration Ready feature for the 1G/2.5G and 1G/2.5G/10G Ethernet design examples.
  • Renamed the document as Intel Arria 10 Low Latency Ethernet 10G MAC Design Example User Guide.
October 2016 2016.10.31
  • Changed the title of the document to be consistent with other design example user guides.
  • Adjusted the rows in the table that describes the design parameters description to match the parameter editor user interface.
  • Updated the steps to run the simulation scripts to clarify that the commands are to be run at the system's command prompt.
  • Updated the simulation script command for VCS and NCSim from "source tb_run.sh" to "sh tb_run.sh".
  • Updated the features of the 10BASE-R design example from supporting single channel to now support dual channels.
  • Added related information links that provide more information about the Avalon-ST and IEEE 1588v2 interface clocks.
May 2016 2016.05.20
  • Updated the Quick Start Guide to include the latest GUI and procedure steps.
  • Updated the Channel Reset diagrams and description for the Multi-speed 10M - 10G and 1G/10G Ethernet design examples.
  • Updated the Clocking diagram the Multi-speed 10M - 10G Ethernet design example with the IEEE 1588v2 feature.
  • Updated the Signal Tap Signals topic for the Multi-speed 10M - 10G, 1G/10G, and 10GBASE-R Ethernet design examples.
  • Updated Chapter 4 to include a 10GBASE-R design example with the Register Mode disabled.
  • Added Chapters 5, 6, and 7, which document 4 new design examples.
  • Updated Interface Signals appendix.
December 2015 2015.12.14 Initial release.
Level Two Title