Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

3.5.1. Test Cases

You can run any of the following tests from the System Console.

Table 12.  Hardware Test Cases
Test Case Command Example
PHY internal serial loopback TEST_PHYSERIAL_LOOPBACK <channel> <speed_test> <burst_size> TEST_PHYSERIAL_LOOPBACK 0 10G 1000
SMA loopback For the design with the IEEE 1588v2 feature:

TEST_SMA_LB <channel> <speed_test> <burst_size>

TEST_SMA_LB 0 10G 1000
For the design without the IEEE 1588v2 feature:

TEST_SMA_LOOPBACK <channel> <speed_test> <burst_size>

Table 13.  Command Parameters
Parameter Valid Values Description
channel 0 to the number of channel specified for the design The number of channels for the test.
speed_test 10G, 1G The PHY speed.
burst_size The number of packets to generate for the test.

When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output.

Figure 25. Sample Test Output—Packet Monitor
Figure 26. Sample Test Output—Statistics Counters