Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

6.7. Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.

Table 26.   Register Map
Byte Offset Block
0x00_0000 Transceiver Reconfiguration
0x00_4000 Reserved
Channel 0
0x01_0000 MAC
0x01_8000 PHY
0x01_A000 Native PHY Reconfiguration
Channel 1
0x02_0000 MAC
0x02_8000 PHY
0x02_A000 Native PHY Reconfiguration
Traffic Controller
0x10_0000 Traffic Controller

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