Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

3.3.1. Design Components

Table 10.  Design Components of the 1G/10G Ethernet Design Example
Component Description
The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
  • Speed: 1G/10G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • All Legacy Ethernet 10G MAC Interfaces options: Selected
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
  • Enable time stamping: Selected
  • Enable PTP one-step clock support: Selected
  • Timestamp fingerprint width: 4
  • Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/10G and 10GBASE-KR PHY Intel® Arria® 10 FPGA IP. The design example uses the 1G/10G IP variant.
Address Decoder Decodes the addresses of the components in each Ethernet channel.
Reset Controller Synchronizes the reset of all design components.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel® FPGA IP. Resets the transceiver.
PLL Generates clocks for all design components.
ATX PLL Generates a TX serial clock for the Intel® Arria® 10 10G transceiver.
FIFO The Avalon® streaming single-clock FIFO. Buffers the RX and TX data between the MAC IP and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH and SC_FIFO_DEPTH parameter values from 512 to 2048, under altera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv.