Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

4.4. Simulation

The simulation test case demonstrates how the MAC and PHY configuration is changed at 10-Gbps throughput. The test case is for a single Ethernet channel.

At the end of the simulation, the simulator generates the statistics of TX and RX packets in the Transcript window.

In the Wave window, the roundtrip latency for the serial loopback is indicated by the measurement cursors that show the time taken to transmit the first data from the TX Avalon® streaming interface to be available at the RX Avalon® streaming interface.