Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

5.3.1. Design Components

Table 21.  Design Components
Component Description

The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:

  • Speed: 1G/2.5G
  • Datapath options: TX & RX
  • Enable ECC on memory blocks: Not selected
  • Enable supplementary address: Selected
  • Enable statistics collection: Selected
  • Statistics counters: Memory-based
  • All Legacy Ethernet 10G MAC Interfaces options: Selected
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
  • Enable time stamping: Selected
  • Enable PTP one-step clock support: Selected
  • Timestamp fingerprint width: 4
  • Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP.
Transceiver Reset Controller The Transceiver PHY Reset Controller Intel® FPGA IP IP. Resets the transceiver.
Avalon® Memory-Mapped Mux Transceiver Reconfig Provides the transceiver reconfig block and system console access to the PHY's Avalon® memory-mapped interface.
Transceiver Reconfig Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa.

Generates a TX serial clock for the Intel® Arria® 10 2.5G transceiver.


Generates a TX serial clock for the Intel® Arria® 10 1G transceiver.

Design Components for the IEEE 1588v2 Feature
IO PLL Generates the clocks for the 1588 design components.
Master TOD The master time-of-day (TOD) for all channels.
TOD Synch Synchronizes the master TOD to all local TODs.
Local TOD The TOD for each channel.
Master Pulse Per Second Returns pulse per second (pps) for all channels.
Pulse Per Second Returns pulse per second (pps) for each channel.
PTP Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP.