Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

9.4. Transceiver Reconfiguration

Table 52.  Transceiver Reconfiguration Register Map
Word Offset Name Bits Description Access HW Reset
0x00 logical_channel_number [9:0] The logical number of the reconfiguration block. RW 0x000
[31:10] Reserved
0x01 control [1:0] Specify the new operating speed:
  • 00: 1 Gbps
  • 01: 2.5 Gbps
  • 10: Reserved
  • 11: 10 Gbps
RW 0x00
[15:2] Reserved 0x000

Writing 1 to this bit when it is 0 starts the reconfiguration process. The bit clears when the process is completed.

RWC 0x0
[31:17] Reserved 0x000000
0x02 status [0] When set to 1, indicates the reconfiguration process is in progress. RO 0x0
[31:1] Reserved

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