Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

9.3.1. 1G/10G PHY

This topic lists the byte offsets of the 1G/10G variant registers for Intel® Arria® 10 devices.

Table 46.  PMA Registers
Byte Offset Bit R/W Name
0x1110 1 RW reset_tx_digital
2 RW reset_rx_analog
3 RW reset_rx_dgital
0x1184 0 RW phy_serial_loopback
0x1190 0 RW pma_rx_set_locktodata
0x1194 0 RW pma_rx_set_locktoref
0x1198 0 RO pma_rx_is_lockedtodata
0x119C 0 RO pma_rx_is_lockedtoref
0x12A0 0 RW tx_invpolarity
1 RW rx_invpolarity
2 RW rx_bitreversal_enable
3 RW rx_bytereversal_enable
4 RW force_electrical_idle
0x12A4 0 R rx_syncstatus
1 R rx_patterndetect
2 R rx_rlv
3 R rx_rmfifodatainserted
4 R rx_rmfifodatadeleted
5 R rx_disperr
6 R rx_errdetect
Table 47.  PCS Registers
Byte Offset Bit R/W Name
0x1200 RW Indirect_addr
0x1204 2 RW RCLR_ERRBLK_CNT
3 RW RCLR_BER_COUNT
0x1208 1 RO HI_BER
2 RO BLOCK_LOCK
3 RO TX_FULL
4 RO RX_FULL
7 RO Rx_DATA_READY
Table 48.   Intel® Arria® 10 GMII PCS Registers
Byte Offset Bit R/W Name
0x1240 9 RW RESTART_AUTO_NEGOTIATION
12 RW AUTO_NEGOTIATION_ENABLE
15 RW RESET
0x1244 2 R LINK_STATUS
3 R AUTO_NEGOTIATION_ ABILITY
5 R AUTO_NEGOTIATION_ COMPLETE
0x1250 5 RW FD
6 RW HD
8:7 RW PS2,PS1
13:12 RW RF2,RF1
14 R0 ACK
15 RW NP
0x1254 5 R FD
6 R HD
8:7 R PS2,PS1
13:12 R RF2,RF1
14 R ACK
15 R NP
0x1258 0 R LINK_PARTNER_AUTO_NEGOTIATION_ABLE
1 R PAGE_RECEIVE
0x1288 15:0 RW AN link timer[15:0]
0x128C 4:0 RW AN link timer[4:0]
0x1290 0 RW SGMII_ENA
1 RW USE_SGMII_AN
3:2 RW SGMII_SPEED

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