Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

2.3. Functional Description

The design examples consist of various components. The following block diagrams show the design components and the top-level signals of the design examples.

Figure 6. Block Diagram—10M/100M/1G/10G Ethernet Design Example without IEEE 1588v2 Feature
Figure 7. Block Diagram—10M/100M/1G/10G Ethernet Design Example with IEEE 1588v2 Feature