Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

5.3. Functional Description

The design example consists of various components. The following block diagrams shows the design components and the top-level signals of the design example.

Figure 34. Block Diagram—1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
Figure 35. Block Diagram—1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature

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