Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

6.3.4. Partial Reconfiguration Ready

When the Partial Reconfiguration Ready option is turned on, the generated hierarchy of the design example is in compliance with the partial reconfiguration flow. There is a clear separation between the hard IP and the soft IP. Hard IPs such as Native PHY, JTAG, transmitter (TX) PLL, and fPLL are instantiated at the top-level wrapper of the design example. Certain soft IPs such as transceiver reset controller and TX PLL reset controller are also instantiated at the top-level wrapper of the design example because their functions are tightly coupled to the hard IPs. A wrapper called alt_eth_pr contains the soft IP logic that you can add to the partial reconfiguration region of your design. There is no functionality change after the Partial Reconfiguration Ready option is turned on.

Figure 51. 1G/2.5G/10G Ethernet Design Example Hierarchy when the Partial Reconfiguration Ready Option is Turned Off
Figure 52. 1G/2.5G/10G Ethernet Design Example Hierarchy when the Partial Reconfiguration Ready Option is Turned On

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