Visible to Intel only — GUID: nfa1447850304179
Ixiasoft
1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
Visible to Intel only — GUID: nfa1447850304179
Ixiasoft
4.7. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
Byte Offset | Block |
---|---|
0x0000_0000 | LL 10GbE MAC |
0x0000_8000 | Native PHY |
0x0000_D400 | RX SC FIFO |
0x0000_D600 | TX SC FIFO |
0x0000_C000 | Packet Generator and Checker |
0x0000_D000 – 0xFFFF_FFFF | Client Logic |