Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

4.7. Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
Table 20.  Register Map
Byte Offset Block
0x0000_0000 LL 10GbE MAC
0x0000_8000 Native PHY
0x0000_D400 RX SC FIFO
0x0000_D600 TX SC FIFO
0x0000_C000 Packet Generator and Checker
0x0000_D000 – 0xFFFF_FFFF Client Logic