Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

7.3.2. Clocking Scheme

Figure 58. Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example

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