Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

4.5.2. Signal Tap Debug Signals

The Signal Tap file is included for debugging.

This feature is disabled by default. To enable it, set the following assignment:

set_global_assignment -name ENABLE_SIGNALTAP ON
Table 19.   Signal Tap Debug Signals
Component Module Name Signal
Top-level design example altera_eth_top
  • csr_clk
  • ref_clk_clk
  • master_reset_n
  • block_lock_n
  • tx_ready_export_n
  • rx_ready_export_n
Design Example altera_eth_top.altera_eth_10g_mac_base_r_low_latency
  • atx_pll_locked
  • iopll_locked
MAC IP core altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac
  • avalon_st_tx_startofpacket
  • avalon_st_tx_endofpacket
  • avalon_st_tx_data
  • avalon_st_tx_ready
  • avalon_st_tx_valid
  • avalon_st_tx_error
  • avalon_st_tx_empty
  • avalon_st_rx_startofpacket
  • avalon_st_rx_endofpacket
  • avalon_st_rx_data
  • avalon_st_rx_ready
  • avalon_st_rx_valid
  • avalon_st_rx_error
  • avalon_st_rx_empty
MAC TX altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_tx_top.alt_em10g32_tx_rs_layer.alt_em10g32_tx_rs_xgmii_layer_ultra
  • xgmii_tx_valid
  • xgmii_tx_data
  • xgmii_tx_control
MAC RX altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_rx_top.alt_em10g32_rx_rs_layer.alt_em10g32_rx_rs_xgmii_ultra
  • xgmii rx valid
  • xgmii rx data
  • xgmii rx control
  • xgmii rx link fault status
PHY altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_baser
  • tx_analogreset
  • tx_digitalreset
  • rx_analogreset
  • rx_digitalreset
  • tx_cal_busy
  • rx_cal_busy
  • rx_is_lockedtodata
  • tx_clkout

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