Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

2.4.2. Test Case—Design Example without the IEEE 1588v2 Feature

The simulation test case performs the following steps:

  1. Starts up the example design with an operating speed of 10G.
  2. Configures the MAC, PHY, and FIFO buffer for all channels.
  3. Waits until the example design asserts the channel_ready signal for each channel.
  4. Sends the following packets:
    • Normal data frame, 64Bytes
    • SVLAN data frame, broadcast, 64Bytes
    • VLAN data frame, unicast, 500Bytes
  5. Repeats steps 2 to 4 for other operating speeds.

When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.

Figure 13. Sample Simulation Output

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