Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

8. Interface Signals Description

Use the following tables to find the description of the signals in the LL 10GbE MAC Intel® FPGA IP design examples. The pinout diagram for each design example specifies the width of the signals.

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