Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Document Table of Contents

4.3.2. Clocking and Reset Scheme

Figure 29. Clocking and Reset Scheme for 10GBASE-R Design Example
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.

Figure 30. Clocking and Reset Scheme for 10GBASE-R Design Example with the Register Mode Enabled

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