Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 19.1 |
| IP Version 19.1 |
1. Quick Start Guide
The Low Latency 10G Ethernet (LL 10GbE) MAC Intel® FPGA IP for Intel® Arria® 10 devices provides the capability of generating design examples for selected configurations.
1.1. Directory Structure
| Directory/File | Description |
|---|---|
| altera_eth_top.qpf | Intel® Quartus® Prime project file. |
| altera_eth_top.qsf | Intel® Quartus® Prime settings file. |
| altera_eth_top.sv | Design example top-level HDL. |
| altera_eth_top.sdc | Synopsys Design Constraints (SDC) file. |
| rtl | The folder that contains the design example synthesizable components. |
|
rtl/altera_eth_10g_mac_base_r.sv rtl/altera_10g_mac_base_r_wrap.v |
Design example DUT top-level files for 10GBASE-R Ethernet design example. |
|
rtl/altera_mge_rd.sv rtl/altera_mge_channel.v |
Design example DUT top-level files for the following
Ethernet
design examples:
|
|
rtl/altera_eth_channel.v rtl/altera_eth_multi_channel.sv |
Design example DUT top-level files for the following
Ethernet
design examples:
|
|
rtl/altera_eth_channel_1588.v rtl/altera_eth_multi_channel_1588.sv |
Design example DUT top-level files for the following
Ethernet
design examples:
|
|
rtl/altera_mge_multi_channel.sv rtl/altera_mge_channel.v |
Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example. |
| rtl/<Design Component> | The folder for each synthesizable component including Platform Designer generated IPs, such as LL 10GbE MAC, PHY, and FIFO. |
| simulation/ed_sim/models | The folder that contains the testbench files. |
|
simulation/ed_sim/cadence simulation/ed_sim/mentor simulation/ed_sim/synopsys/vcs simulation/ed_sim/xcelium |
The folder that contains the simulation script. It also serves as a working area for the simulator. |
| hwtesting/system_console | The folder that contains system console scripts for hardware testing. |
| output_files | The folder that contains Intel® Quartus® Prime output files including Intel® Quartus® Prime compilation reports and design programing file (.sof file). |
1.2. Generating the Design
1.2.1. Procedure
1.2.2. Design Example Parameters
| Parameter | Description |
|---|---|
| Select Design | Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design. |
| Example Design Files |
The files to generate for the different development phase.
|
| Generate File Format | The format of the RTL files for simulation—Verilog or VHDL. |
| Select Board | Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit. If this menu is not available, there is no supported board for the options that you select. Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit : This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device to match the device on the Intel® FPGA IP development kit. If your board revision has a different device grade, you can change the target device. Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel® FPGA IP device, a custom designed board with Intel® FPGA IP device, or a standard Intel® FPGA IP development kit not available for selection. You can also select a custom device for the custom development kit. No Development Kit: This option excludes the hardware aspects for the design example. |
| Change Target Device | Select this parameter to display and select all devices for the Intel® FPGA IP development kit. |
| Specify Number of Channels | The number of Ethernet channels. |
| Enable Native PHY Debug Master Endpoint (NPDME) | Turn on this option to enable the Transceiver Native PHY Debug Master Endpoint (NPDME) feature. Note: This option is only available from
Intel®
Quartus® Prime Pro Edition version 17.0
onwards
|
| Partial Reconfiguration Ready | When this option is enabled, the generated hierarchy of the design example is compliance with the partial reconfiguration flow, where there is clear separation between hard IP and soft IP, without any functionality changes. Hard IPs such as Native PHY, JTAG, transmitter PLL, and FPLL are instantiated at the top-level wrapper of design example. Note: This option is only available from
Intel®
Quartus® Prime Pro Edition version 17.1 onwards
|
1.3. Compiling and Simulating the Design
1.3.1. Procedure
Simulation stopped due to successful completion! Simulation passed.
1.3.2. Testbench
| Component | Description |
|---|---|
| Device under test (DUT) | The design example. |
| Avalon® driver | Consists of Avalon® streaming master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon® memory-mapped interface of the DUT. |
| Ethernet packet monitors | Monitor TX and RX datapaths, and display the frames in the simulator console. |
1.4. Compiling and Testing the Design in Hardware
1.4.1. Procedure
1.4.2. Hardware Setup
2. 10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices
The 10M/100M/10G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at various speeds.
Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature.
2.1. Features
- Multi-speed Ethernet operation—10M, 100M, 1G, and 10G.
- Support for up to 12 channels.
- Packet monitoring on the TX and RX datapaths.
- Option to generate the design example with the IEEE 1588v2 feature.
- Tested with the Spirent TestCenter.
2.2. Hardware and Software Requirements
- Intel® Quartus® Prime software
- ModelSim* -AE, ModelSim* -SE, NCSim (Verilog only), VCS, and Xcelium* ( Intel® Quartus® Prime Pro Edition only) simulators
- Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit for hardware testing
2.3. Functional Description
The design examples consist of various components. The following block diagrams show the design components and the top-level signals of the design examples.
2.3.1. Design Components
| Component | Description | |
|---|---|---|
| LL 10GbE MAC |
The Low Latency Ethernet 10G MAC
Intel® FPGA IP with the following configuration:
For the design example with the IEEE 1588v2 feature, the following
additional parameters are configured:
|
|
| PHY | The 1G/10G and 10GBASE-KR PHY Intel® Arria® 10 FPGA IP. The design example uses the 1G/10G IP variant. | |
| Address decoder | Decodes the addresses of the components in each Ethernet channel. | |
| Multi-channel address decoder | Decodes the addresses of the components used by all channels, such as the Master TOD module. | |
| Reset controller | Synchronizes the reset of all design components. | |
| Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP. Resets the transceiver. | |
| PLL | Generates clocks for all design components. | |
| ATX PLL | Generates a TX serial clock for the Intel® Arria® 10 10G transceiver. | |
| fPLL | Generates a TX serial clock for the Intel® Arria® 10 1G transceiver. | |
| MDIO | Provides an MDIO interface to the external PHY. | |
| FIFO | The Avalon® streaming single-clock FIFO. Buffers the RX and TX data between the MAC IP and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH and SC_FIFO_DEPTH parameter values from 512 to 2048, under altera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv. | |
| Design Components for the IEEE 1588v2 Feature | ||
| Master TOD | The master TOD for all channels. | |
| TOD Sync | Synchronizes the Master TOD to all Local TODs. | |
| Local TOD | The TOD for each channel. | |
| Master Pulse Per Second | Returns pulse per second (pps) for all channels. | |
| Pulse Per Second | Returns pulse per second (pps) for each channel. | |
| PTP packet classifier | Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP. | |
2.3.2. Clocking Scheme
The following diagrams show the clocking scheme for the design example.
2.3.3. Reset Scheme
The reset signals of the design example—master_reset_n and channel_reset_n[n:0]—are asynchronous and active-low signals. Asserting the master_reset_n signal resets all channels and their components; asserting the channel_reset_n[n] signal resets only the n channel and its components.
Upon power-up, reset the example design by asserting the master_reset_n signal. The following diagram shows the master reset scheme for the design example.
The following diagram shows the channel reset scheme for the design example. The mm_reset signal is used to reset the registers of the design components, whereas the datapath_reset is used to reset all digital blocks including the transceiver reset controller. The mm_reset and datapath_reset are triggered at the same time because they are tied together.
The reset csr block triggers the MAC reset only when the PHY's speed changes, which is indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link is lost, you can set the parameter PHY2MAC_RESET_EN to 1 in altera_eth_channel_1588.v/altera_eth_channel.sv
2.4. Simulation
| Operation | Description |
|---|---|
| Configuring the PHY speed. | Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), 1G1000Base-X or 1G/100M/10M SGMII. |
| Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X. | Write one of the following values to the PHY's register at address offset
0x12C0.
Example To set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11 To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01 |
| Changing the speed between 1 Gbps, 100 Mbps, and 10 Mbps in SGMII. |
|
2.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following steps:
- Starts up the design example with an operating speed of 10G.
- Configures the MAC, PHY, and FIFO buffer for all channels.
- Waits until the design example asserts the channel_ready signal for each channel.
- Sends the following packets:
- Non-PTP
- No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
- No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
- Repeats steps 2 to 4 for other operating speeds.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
2.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
The simulation test case performs the following steps:
- Starts up the example design with an operating speed of 10G.
- Configures the MAC, PHY, and FIFO buffer for all channels.
- Waits until the example design asserts the channel_ready signal for each channel.
- Sends the following packets:
- Normal data frame, 64Bytes
- SVLAN data frame, broadcast, 64Bytes
- VLAN data frame, unicast, 500Bytes
- Repeats steps 2 to 4 for other operating speeds.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
2.5. Hardware Testing
- Y5—644.53125 MHz
- Y6—125 MHz
2.5.1. Test Cases
You can run any of the following tests from the System Console.
| Test Case | Command | Example |
|---|---|---|
| PHY internal serial loopback | TEST_PHYSERIAL_LOOPBACK <channel> <speed_test> <burst_size> | TEST_PHYSERIAL_LOOPBACK 0 10G 1000 |
| SMA loopback | For the design with the IEEE 1588v2 feature: TEST_SMA_LB <channel> <speed_test> <burst_size> |
TEST_SMA_LB 0 10G 1000 |
| For the design without the IEEE 1588v2
feature: TEST_SMA_LOOPBACK <channel> <speed_test> <burst_size> |
| Parameter | Valid Values | Description |
|---|---|---|
| channel | 0 to the number of channel specified for the design | The number of channels for the test. |
| speed_test | 10G, 1G, 100M, 10M | The PHY speed. |
| burst_size | — | The number of packets to generate for the test. |
When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output.
2.5.2. Signal Tap Debug Signals
The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below:
set_global_assignment -name ENABLE_SIGNALTAP ON
| Component | Module Name | Signal |
|---|---|---|
| Top-level design example | altera_eth_top |
|
| Multi-channel wrapper |
Design example without the IEEE 1588v2 feature: altera_eth_top.altera_eth_multi_channel Design example with the IEEE 1588v2 feature: altera_eth_top.altera_eth_multi_channel_1588 |
|
| MAC IP | <n>.altera_eth_10g_mac 2 |
|
| PHY | <n>.altera_eth_10gkr_phy 2 |
|
| XGMII | <n>.altera_eth_10g_mac.alt_em10g32.alt_em10g32unit 2 |
|
| GMII | <n>.altera_eth_10g_mac 2 |
|
| MII | <n>.altera_eth_10g_mac 2 |
|
- altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design example without the IEEE 1588v2 feature.
- altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588 for the design example with the IEEE 1588v2 feature.
2.6. Interface Signals
2.7. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
| Byte Offset | Block |
|---|---|
| 0x00_0000 | Client logic |
| 0x00_F000 | Reserved |
| 0x01_0000 | Master TOD |
| Channel 0 | |
| 0x02_0000 | Reserved |
| 0x02_4000 | PHY |
| 0x02_7800 | 10G TOD |
| 0x02_7900 | 1G TOD |
| 0x02_8000 | LL 10GbE MAC |
| Channel 1 | |
| 0x03_0000 | Reserved |
| 0x03_4000 | PHY |
| 0x03_7800 | 10G TOD |
| 0x03_7900 | 1G TOD |
| 0x03_8000 | LL 10GbE MAC |
| .. and so forth up to Channel 11. | |
| 0x0E_0000 onwards | Client Logic |
3. 1G/10G Ethernet Design Example for Intel Arria 10 Devices
The 1G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 1G and 10G.
Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature.
3.1. Features
- Dual-speed Ethernet operation—1G and 10G.
- Support for up to 12 channels.
- Packet monitoring on the TX and RX datapaths.
- Option to generate the design example with the IEEE 1588v2 feature.
- Tested with the Spirent TestCenter.
3.2. Hardware and Software Requirements
- Intel® Quartus® Prime software
- ModelSim* -AE, ModelSim* -SE, NCSim (Verilog only), VCS, and Xcelium* ( Intel® Quartus® Prime Pro Edition only) simulators
- Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit for hardware testing
3.3. Functional Description
The design example consists of various components. The following block diagrams show the design components and the top-level signals of the design example.
3.3.1. Design Components
| Component | Description |
|---|---|
| LL 10GbE MAC |
The Low Latency Ethernet 10G MAC
Intel® FPGA IP with the following configuration:
For the
design
example
with the IEEE 1588v2 feature, the following additional parameters
are configured:
|
| PHY | The 1G/10G and 10GBASE-KR PHY Intel® Arria® 10 FPGA IP. The design example uses the 1G/10G IP variant. |
| Address Decoder | Decodes the addresses of the components in each Ethernet channel. |
| Reset Controller | Synchronizes the reset of all design components. |
| Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP. Resets the transceiver. |
| PLL | Generates clocks for all design components. |
| ATX PLL | Generates a TX serial clock for the Intel® Arria® 10 10G transceiver. |
| FIFO | The Avalon® streaming single-clock FIFO. Buffers the RX and TX data between the MAC IP and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH and SC_FIFO_DEPTH parameter values from 512 to 2048, under altera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv. |
3.3.2. Clocking Scheme
The following diagrams show the clocking scheme for the design example.
3.3.3. Reset Scheme
The reset signals of the design example—master_reset_n and channel_reset_n[n:0]—are asynchronous and active-low signals. Asserting the master_reset_n signal resets all channels and their components; asserting the channel_reset_n[n] signal resets only the n channel and its components.
Upon power-up, reset the example design by asserting the master_reset_n signal. The following diagram shows the master reset scheme for the design example.
The following diagram shows the channel reset scheme for the design example. The mm_reset signal is used to reset the registers of the design components, whereas the datapath_reset is used to reset all digital blocks including the transceiver reset controller. The mm_reset and datapath_reset are triggered at the same time because they are tied together.
The reset csr block triggers the MAC reset only when the PHY's speed changes, which is indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link is lost, you can set the parameter PHY2MAC_RESET_EN to 1 in altera_eth_channel_1588.v/altera_eth_channel.sv
3.4. Simulation
| Operation | Description |
|---|---|
| Configuring the PHY speed. | Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), or 1G1000Base-X. |
| Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X. | Write one of the following values to the PHY's register at address offset
0x12C0.
Example To set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11 To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01 |
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following steps:
- Starts up the design example with an operating speed of 10G.
- Configures the MAC, PHY, and FIFO buffer for all channels.
- Waits until the design example asserts the channel_ready signal for each channel.
- Sends the following packets:
- Non-PTP
- No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
- No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
- Repeats steps 2 to 4 for other operating speeds.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
The simulation test case performs the following steps:
- Starts up the example design with an operating speed of 10G.
- Configures the MAC, PHY, and FIFO buffer for all channels.
- Waits until the example design asserts the channel_ready signal for each channel.
- Sends the following packets:
- Normal data frame, 64Bytes
- SVLAN data frame, broadcast, 64Bytes
- VLAN data frame, unicast, 500Bytes
- Repeats steps 2 to 4 for other operating speeds.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
3.5. Hardware Testing
- Y5—644.53125 MHz
- Y6—125 MHz
3.5.1. Test Cases
You can run any of the following tests from the System Console.
| Test Case | Command | Example |
|---|---|---|
| PHY internal serial loopback | TEST_PHYSERIAL_LOOPBACK <channel> <speed_test> <burst_size> | TEST_PHYSERIAL_LOOPBACK 0 10G 1000 |
| SMA loopback | For the design with the IEEE 1588v2 feature: TEST_SMA_LB <channel> <speed_test> <burst_size> |
TEST_SMA_LB 0 10G 1000 |
| For the design without the IEEE 1588v2
feature: TEST_SMA_LOOPBACK <channel> <speed_test> <burst_size> |
| Parameter | Valid Values | Description |
|---|---|---|
| channel | 0 to the number of channel specified for the design | The number of channels for the test. |
| speed_test | 10G, 1G | The PHY speed. |
| burst_size | — | The number of packets to generate for the test. |
When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output.
3.5.2. Signal Tap Debug Signals
The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below:
set_global_assignment -name ENABLE_SIGNALTAP ON
| Component | Module Name | Signal |
|---|---|---|
| Top-level design example | altera_eth_top |
|
| Multi-channel wrapper |
Design example without the IEEE 1588v2 feature: altera_eth_top.altera_eth_multi_channel Design example with the IEEE 1588v2 feature: altera_eth_top.altera_eth_multi_channel_1588 |
|
| MAC IP core | <n>.altera_eth_10g_mac 3 |
|
| PHY | <n>.altera_eth_10gkr_phy 3 |
|
| XGMII | <n>.altera_eth_10g_mac.alt_em10g32.alt_em10g32unit 3 |
|
| GMII | <n>.altera_eth_10g_mac 3 |
|
- altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design example without the IEEE 1588v2 feature.
- altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588 for the design example with the IEEE 1588v2 feature.
3.6. Interface Signals
| Clock | Frequency (MHz) | Interface Signals |
|---|---|---|
| xgmii_clk | 156.25 |
|
| mm_clk | 125 |
|
| pll_ref_clk_1g | 125 |
|
3.7. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
| Byte Offset | Block |
|---|---|
| 0x00_0000 | Client logic |
| 0x00_F000 | Reserved |
| 0x01_0000 | Master TOD |
| Channel 0 | |
| 0x02_0000 | Reserved |
| 0x02_4000 | PHY |
| 0x02_7800 | 10G TOD |
| 0x02_7900 | 1G TOD |
| 0x02_8000 | LL 10GbE MAC |
| Channel 1 | |
| 0x03_0000 | Reserved |
| 0x03_4000 | PHY |
| 0x03_7800 | 10G TOD |
| 0x03_7900 | 1G TOD |
| 0x03_8000 | LL 10GbE MAC |
| .. and so forth up to Channel 11. | |
| 0x0E_0000 onwards | Client Logic |
4. 10GBASE-R Ethernet Design Example for Intel Arria 10 Devices
Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor.
4.1. Features
- Supports single Ethernet channels operating at 10G using Intel® Arria® 10 Native PHY.
- Option to generate the design example with the 10GBASE-R register mode enabled.
- 140 ns round-trip latency in simulation when the register mode is enabled.
- Packet monitoring on the TX and RX datapaths.
- Tested with the Spirent TestCenter.
4.2. Hardware and Software Requirements
Intel® uses the following hardware and software to test the design example in a Linux system:
- Intel® Quartus® Prime software
- ModelSim* -AE, ModelSim* -SE, NCSim (Verilog only), VCS, and Xcelium* ( Intel® Quartus® Prime Pro Edition only) simulators
- For hardware testing:
- Intel® Arria® 10 GX Transceiver Signal Integrity Development Kit
- Cables—SFP+ and fiber optic cable
4.3. Functional Description
4.3.1. Design Components
| Component | Description | |
|---|---|---|
| LL 10GbE MAC |
The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
The settings when the 10GBASE-R Register mode is enabled:
|
|
| PHY |
|
|
| Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP . Resets the transceiver. | |
| Address decoder | Decodes the addresses of the components. | |
| Reset synchronizer | Synchronizes the reset of all design components. | |
| ATX PLL |
Generates a TX serial clock for the Intel® Arria® 10 10G transceiver. |
|
| FIFO |
|
|
4.3.2. Clocking and Reset Scheme
4.4. Simulation
At the end of the simulation, the simulator generates the statistics of TX and RX packets in the Transcript window.
In the Wave window, the roundtrip latency for the serial loopback is indicated by the measurement cursors that show the time taken to transmit the first data from the TX Avalon® streaming interface to be available at the RX Avalon® streaming interface.
4.5. Hardware Testing
In the Clock Control application, which is part of the development kit, set the following frequencies:
- Y5—322.265625 MHz
- Y6—125 MHz
4.5.1. Test Cases
You can run any of the following tests from the System Console.
| Test Case | Command | Description |
|---|---|---|
|
SFP+ loopback |
source gen_conf.tcl |
The generator generates and sends about 4 billion packets. Wait 6 minutes for it to complete its tasks. |
| source monitor_conf.tcl | The monitor checks the number of good and bad packets received. | |
| source show_stats.tcl | This script displays the values of the statistics counters. | |
| Avalon® streaming interface loopback | source loopback_conf.tcl | This command enables the Avalon® streaming interface loopback. This test is used with an external tester such as Spirent tester. |
After the test is completed, observe the output displayed in the System Console.
4.5.2. Signal Tap Debug Signals
This feature is disabled by default. To enable it, set the following assignment:
set_global_assignment -name ENABLE_SIGNALTAP ON
| Component | Module Name | Signal |
|---|---|---|
| Top-level design example | altera_eth_top |
|
| Design Example | altera_eth_top.altera_eth_10g_mac_base_r_low_latency |
|
| MAC IP core | altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac |
|
| MAC TX | altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_tx_top.alt_em10g32_tx_rs_layer.alt_em10g32_tx_rs_xgmii_layer_ultra |
|
| MAC RX | altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_rx_top.alt_em10g32_rx_rs_layer.alt_em10g32_rx_rs_xgmii_ultra |
|
| PHY | altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_baser |
|
4.6. Interface Signals
4.7. Configuration Registers
| Byte Offset | Block |
|---|---|
| 0x0000_0000 | LL 10GbE MAC |
| 0x0000_8000 | Native PHY |
| 0x0000_D400 | RX SC FIFO |
| 0x0000_D600 | TX SC FIFO |
| 0x0000_C000 | Packet Generator and Checker |
| 0x0000_D000 – 0xFFFF_FFFF | Client Logic |
5. 1G/2.5G Ethernet Design Example for Intel Arria 10 Devices
The 1G/2.5G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 1G and 2.5G.
Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature.
5.1. Features
- Dual-speed Ethernet operation—1G and 2.5G.
- Support for two channels.
- Option to generate the design example with the IEEE 1588v2 feature.
- Testbench and simulation script.
- Tested with the Spirent TestCenter.
- Option to generate design example with Partial Reconfiguration Ready.
5.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linux system:
- Intel® Quartus® Prime Pro Edition software (Partial Reconfiguration Ready)
- ModelSim* -AE, ModelSim* -SE, NCSim (Verilog only), VCS, and Xcelium* ( Intel® Quartus® Prime Pro Edition only) simulators
- For hardware testing:
- Intel® Arria® 10 GX Signal Integrity Development Board (10AX115S3F45E2SGE3)—for the design example with the IEEE 1588v2 feature
- Intel® Arria® 10 GX Signal Integrity Development Board (10AX115S4F45E3SGE3)—for the design example without the IEEE 1588v2 feature
5.3. Functional Description
The design example consists of various components. The following block diagrams shows the design components and the top-level signals of the design example.
5.3.1. Design Components
| Component | Description |
|---|---|
| LL 10GbE MAC |
The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
For the
design
example
with the IEEE 1588v2 feature, the following additional parameters
are configured:
|
| PHY | The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP. |
| Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP IP. Resets the transceiver. |
| Avalon® Memory-Mapped Mux Transceiver Reconfig | Provides the transceiver reconfig block and system console access to the PHY's Avalon® memory-mapped interface. |
| Transceiver Reconfig | Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa. |
| ATX PLL |
Generates a TX serial clock for the Intel® Arria® 10 2.5G transceiver. |
| fPLL |
Generates a TX serial clock for the Intel® Arria® 10 1G transceiver. |
| Design Components for the IEEE 1588v2 Feature | |
| IO PLL | Generates the clocks for the 1588 design components. |
| Master TOD | The master time-of-day (TOD) for all channels. |
| TOD Synch | Synchronizes the master TOD to all local TODs. |
| Local TOD | The TOD for each channel. |
| Master Pulse Per Second | Returns pulse per second (pps) for all channels. |
| Pulse Per Second | Returns pulse per second (pps) for each channel. |
| PTP Packet Classifier | Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP. |
5.3.2. Clocking Scheme
5.3.3. Reset Scheme
The global reset signal of the design example is asynchronous and active-low. Asserting this signal resets all channels and their components. Upon power-up, reset the design example.
5.3.4. Partial Reconfiguration Ready
When the Partial Reconfiguration Ready option is turned on, the generated hierarchy of the design example is in compliance with the partial reconfiguration flow. There is a clear separation between the hard IP and the soft IP. Hard IPs such as Native PHY, JTAG, transmitter (TX) PLL, and fPLL are instantiated at the top-level wrapper of the design example. Certain soft IPs such as transceiver reset controller and TX PLL reset controller are also instantiated at the top-level wrapper of the design example because their functions are tightly coupled to the hard IPs. A wrapper called alt_eth_pr contains the soft IP logic that you can add to the partial reconfiguration region of your design. There is no functionality change after the Partial Reconfiguration Ready option is turned on.
5.4. Simulation
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following steps:
- Starts up the design example with an operating speed of 2.5G.
- Configures the MAC, PHY, and FIFO buffer for both channels.
- Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for each channel.
- Sends the following packets:
- Non-PTP
- No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
- VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
- No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
- Repeats steps 2 to 4 for 1G.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
5.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
The simulation test case performs the following steps:
- Starts up the example design with an operating speed of 2.5G.
- Configures the MAC, PHY, and FIFO buffer for both channels.
- Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for both channels.
- Sends the following packets:
- 64-byte packet
- 1518-byte packet
- 100-byte packet
- Repeats steps 2 to 4 for 1G.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
5.5. Hardware Testing
- Y5—644.53125 MHz
- Y6—125 MHz
5.5.1. Test Procedure
Follow these steps to test the design examples in hardware:
- Run the following command in the system console to start the
test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 2.5G 1000000000
Table 22. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G The PHY speed. burst_size An integer value The number of packets to generate for the test. - When the test is completed, observe the output displayed. The following
diagrams show excerpts of the output, which shows that the Ethernet packet monitor block
receives the same number of packets generated without error, and the TX and RX statistics
counters.Figure 45. Sample Test Output—Ethernet Packet Monitor
Figure 46. Sample Test Output—Statistics Counters
5.6. Interface Signal
5.7. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
| Byte Offset | Block |
|---|---|
| 0x00_0000 | Transceiver Reconfiguration |
| 0x00_4000 | Reserved |
| Channel 0 | |
| 0x01_0000 | MAC |
| 0x01_8000 | PHY |
| 0x01_A000 | Native PHY Reconfiguration |
| Channel 1 | |
| 0x02_0000 | MAC |
| 0x02_8000 | PHY |
| 0x02_A000 | Native PHY Reconfiguration |
| Traffic Controller | |
| 0x10_0000 | Traffic Controller |
6. 1G/2.5G/10G Ethernet Design Example for Intel Arria 10 Devices
The 1G/2.5G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 1G, 2.5G, and 10G.
Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor.
6.1. Features
- Tri-speed Ethernet operation—1G, 2.5G, and 10G.
- Support for two channels.
- Testbench and simulation script.
- Tested with the Spirent TestCenter.
- Option to generate design example with Partial Reconfiguration Ready.
6.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linux system:
- Intel® Quartus® Prime Pro Edition software (Partial Reconfiguration Ready)
- ModelSim* -AE, ModelSim* -SE, NCSim (Verilog only), VCS, and Xcelium* ( Intel® Quartus® Prime Pro Edition only) simulators
- For hardware testing:
- Intel® Arria® 10 GX Signal Integrity Development Board (10AX115S4F45E3SGE3)
- Cables—SMA cable, SFP+, and fiber optic cable
6.3. Functional Description
The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.
6.3.1. Design Components
| Component | Description |
|---|---|
| LL 10GbE MAC |
The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
|
| PHY | The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP. |
| Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP. Resets the transceiver. |
| Avalon® Memory-Mapped Mux Transceiver Reconfig | Provides the transceiver reconfig block and system console access to the PHY's Avalon® memory-mapped interface. |
| Transceiver Reconfig | Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa. |
| ATX PLL | Generates a TX serial clock for the Intel® Arria® 10 2.5G and 10G transceiver. |
| fPLL | Generates a TX serial clock for the Intel® Arria® 10 1G transceiver. |
6.3.2. Clocking Scheme
6.3.3. Reset Scheme
The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example.
6.3.4. Partial Reconfiguration Ready
When the Partial Reconfiguration Ready option is turned on, the generated hierarchy of the design example is in compliance with the partial reconfiguration flow. There is a clear separation between the hard IP and the soft IP. Hard IPs such as Native PHY, JTAG, transmitter (TX) PLL, and fPLL are instantiated at the top-level wrapper of the design example. Certain soft IPs such as transceiver reset controller and TX PLL reset controller are also instantiated at the top-level wrapper of the design example because their functions are tightly coupled to the hard IPs. A wrapper called alt_eth_pr contains the soft IP logic that you can add to the partial reconfiguration region of your design. There is no functionality change after the Partial Reconfiguration Ready option is turned on.
6.3.5. Timing Constraints
When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intel® recommends that you refer to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core section of Intel® Arria® 10 Transceiver PHY User Guide for details on the timing constraint examples.
set_false_path -from [get_clocks "$rx_pma_clk_10g_name $rx_clkout_10g_name $tx_pma_clk_10g_name $tx_clkout_10g_name"] -to [get_registers *|alt_em10g32:*|*] set_false_path -from [get_registers *|alt_em10g32:*|*] -to [get_clocks "$rx_pma_clk_10g_name $rx_clkout_10g_name $tx_pma_clk_10g_name $tx_clkout_10g_name"]where the path indicated by rx_pma_clk_10g_name, rx_clkout_10g_name, tx_clkout_10g_name, and tx_clkout_10g_name is associated with the 10G PHY clock, whereas the alt_em10g32 path indicates the LL 10GbE MAC logic.
6.4. Simulation
The simulation test case performs the following steps:
- Starts up the example design with an operating speed of 10 Gbps.
- Configures the MAC, PHY, and FIFO buffer for both channels.
- Waits until the design example asserts the channel_tx_ready and channel_rx_readysignals for both channels.
- Sends the following packets:
- 64-byte packet
- 1518-byte packet
- 100-byte packet
- Repeats steps 2 to 4 for 1G and 2.5G.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
6.5. Hardware Testing
- Y5—644.53125 MHz
- Y6—125 MHz
6.5.1. Test Procedure
Follow these steps to test the design examples in hardware:
- Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 10G 80000000
Table 25. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. - When the test is completed, observe the output displayed. The following
diagrams show excerpts of the output, which shows that the packet monitor block receives the
same number of packets generated without error, and the TX and RX statistics counters.Figure 54. Sample Test Output—Packet Monitor
Figure 55. Sample Test Output—Statistics Counters
6.6. Interface Signals
6.7. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
| Byte Offset | Block |
|---|---|
| 0x00_0000 | Transceiver Reconfiguration |
| 0x00_4000 | Reserved |
| Channel 0 | |
| 0x01_0000 | MAC |
| 0x01_8000 | PHY |
| 0x01_A000 | Native PHY Reconfiguration |
| Channel 1 | |
| 0x02_0000 | MAC |
| 0x02_8000 | PHY |
| 0x02_A000 | Native PHY Reconfiguration |
| Traffic Controller | |
| 0x10_0000 | Traffic Controller |
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel Arria 10 Devices
The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel® FPGA IP core operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.
Generate the design example from the Example Design tab of the LL 10GbE Intel® FPGA IP parameter editor.
7.1. Features
- Supports dual Ethernet channel operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.
- On the transmit and receive paths:
- Provides packet monitoring system.
- Reports Ethernet MAC statistics counter.
- Supports testing using different types of Ethernet packet transfer protocol.
7.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linux system:
- Intel® Quartus® Prime software
- ModelSim* -AE, ModelSim* -SE, NCSim (Verilog only), VCS, and Xcelium* ( Intel® Quartus® Prime Pro Edition only) simulators
- For hardware testing:
- Intel® Arria® 10 GX Signal Integrity Development Board (10AX115S4F45E3SGE3)
- Cables—SFP+ and fiber optic cable
7.3. Functional Description
The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.
7.3.1. Design Components
| Component | Description |
|---|---|
| LL 10GbE MAC |
The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
|
| PHY | The 1G/2.5G/5G/10G Multi-rate Ethernet PHY
Intel® FPGA IP with the following configuration:
|
| Channel address decoder | Decodes the addresses of the components in each Ethernet channel, such as PHY and LL 10GbE MAC. |
| Multi-channel address decoder | Decodes the addresses of the components used by all channels , such as the Master ToD module. |
| Top address decoder | Decodes the addresses of the top-level components, such as the Traffic Controller. |
| Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP . Resets the transceiver. |
| ATX PLL | Generates a TX serial clock for the Intel® Arria® 10 10G transceiver. |
| Core fPLL | Generates clocks for all design components. |
7.3.2. Clocking Scheme
7.3.3. Reset Scheme
The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example.
7.4. Simulation
7.4.1. Test Case
The simulation test case performs the following steps:
- Starts up the example design with an operating speed of 10G.
- Configures the MAC, PHY, and FIFO buffer for both channels.
- Waits until the design example asserts the channel_tx_ready and channel_rx_readysignals for both channels.
- Sends the following packets:
- 64-byte packet
- 1518-byte packet
- 100-byte packet
- Repeats steps 2 to 4 for 10M, 100M, 1G, 2.5G, and 5G.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
7.5. Hardware Testing
In the Clock Control application, which is part of the development kit, set the following frequencies:
- Y5—644.53125 MHz
- Y6—125 MHz
7.5.1. Test Procedure
Follow these steps to test the design examples in hardware:
- Run the following command in the system console to enable
PHY serial loopback on Channel 0:
SET_CHANNEL_BASE_ADDR 0
SETPHY_SERIAL_LLPBK
Note: This step is only required if you are using Intel® Arria® 10 GX SI Development Board rev E and above, and on Channel 0 only. - Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 10G 80000000
Table 28. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 10M, 100M, 1G, 2P5G, 5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. - When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the Ethernet packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters.
7.6. Interface Signals
7.7. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
| Byte Offset | Block |
|---|---|
| 0x00_0000 | Reserved |
| Channel 0 | |
| 0x02_0000 | Reserved |
| 0x02_4000 | PHY |
| 0x02_6000 | Native PHY Reconfiguration |
| 0x02_8000 | MAC |
| Channel 1 | |
| 0x03_0000 | Reserved |
| 0x03_4000 | PHY |
| 0x03_6000 | Native PHY Reconfiguration |
| 0x03_8000 | MAC |
| Traffic Controller | |
| 0x10_0000 | Traffic Controller |
8. Interface Signals Description
Use the following tables to find the description of the signals in the LL 10GbE MAC Intel® FPGA IP design examples. The pinout diagram for each design example specifies the width of the signals.
8.1. Clock and Reset Interface Signals
| Signal | Direction | Width | Description |
|---|---|---|---|
|
mm_clk csr_clk |
In | 1 | 125-MHz configuration clock for the Avalon® memory-mapped interface. |
|
mac_clk |
In | 1 | 156.25-MHz configuration clock for the Avalon® streaming interface. |
| refclk | In | 1 | 125-MHz reference clock for the TX PLLs. |
| pll_ref_clk_1g[] | In | [NUM_UNSHARED_CHANNELS] | Reference clock for the TX PLL in 1G mode. Frequency is 125 MHz. |
| pll_ref_clk_10g[] | In | [NUM_UNSHARED_CHANNELS] | Reference clock for the TX PLL in 10G mode. Frequency is 644.53125 MHz. |
| cdr_ref_clk_1g[] | In | [NUM_UNSHARED_CHANNELS] | Reference clock for the RX PLL in 1G mode. Frequency is 125 MHz. |
| cdr_ref_clk_10g[] | In | [NUM_UNSHARED_CHANNELS] | Reference clock for the RX PLL in 10G mode. Frequency is 644.53125 MHz. |
| xgmii_clk | Out | [NUM_UNSHARED_CHANNELS] | Clock used for single data rate (SDR) XGMII TX and RX interface in between MAC and PHY. Whenever present, this clock is also used for Avalon® streaming interface. Frequency is 156.25 MHz. |
| rx_pma_clkout | Out | 1 | CDR recovered clock. |
| rx_recovered_clk | Out | [NUM_CHANNELS] | RX clock, recovered from the RX data. |
| tx_xcvr_clk | Out | 1 | 322.265625-MHz clock for the TX datapath. |
| rx_xcvr_clk | Out | 1 | 322.265625-MHz clock for the RX datapath. |
| iopll_half_clk | Out | 1 | 161.133-MHz synchronous clock derived from ref_clk_clk. |
| ref_clk_clk | In | 1 | 322.265625-MHz clock for the TX PLL. |
| core_clk_312 | Out | 1 | 312.5-MHz clock for the fast domain. |
| core_clk_156 | Out | 1 | 156.25-MHz clock for the slow domain. |
| channel_reset_n | In | [NUM_CHANNELS] | Assert this asynchronous and active-low signal to reset individual Ethernet channel. This does not impact the components running at multi_channel level, for example, master TOD, master PPS, and fPLLs. |
| master_reset_n | In | 1 | Assert this asynchronous and active-low signal to reset the whole design example. |
| reset | In | 1 | Assert this asynchronous and active-high signal to reset the whole design example. |
| csr_rst_n | In | 1 | Active-low reset signal for the Avalon® memory-mapped interface. |
| tx_rst_n | In | 1 | Active-low reset signal for the TX datapath. |
| rx_rst_n | In | 1 | Active-low reset signal for the RX datapath. |
| tx_digitalreset | In | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PCS TX portion of the transceiver PHY. |
| rx_digitalreset | In | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PCS RX portion of the transceiver PHY. |
| tx_analogreset | In | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PMA TX portion of the transceiver PHY. |
| rx_analogreset | In | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PMA RX portion of the transceiver PHY. |
8.2. Avalon Memory-Mapped Interface Signals
| Signal | Direction | Description |
|---|---|---|
|
write csr_mac_write csr_phy_write csr_rcfg_write csr_native_phy_rcfg_write csr_master_tod_write csr_mch_write |
In | Assert this signal to request a write. |
|
read csr_mac_read csr_phy_read csr_rcfg_read csr_native_phy_rcfg_read csr_master_tod_read csr_mch_read |
In | Assert this signal to request a read. |
|
address csr_mac_address csr_phy_address csr_rcfg_address csr_native_phy_rcfg_address csr_master_tod_address csr_mch_address |
In | Use this bus to specify the register address you want to read from or write to. |
|
writedata csr_mac_writedata csr_phy_writedata csr_rcfg_writedata csr_native_phy_rcfg_writedata csr_master_tod_writedata csr_mch_writedata |
In | Carries the data to be written to the specified register. |
|
readdata csr_mac_readdata csr_phy_readdata csr_rcfg_readdata csr_native_phy_rcfg_readdata csr_master_tod_readdata csr_mch_readdata |
Out | Carries the data read from the specified register. |
|
waitrequest csr_mac_waitrequest csr_phy_waitrequest csr_native_phy_rcfg_waitrequest csr_master_tod_waitrequest csr_mch_waitrequest |
Out | When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests. |
8.3. Avalon Streaming Interface Signals
| Signal | Direction | Width | Description |
|---|---|---|---|
| avalon_st_tx_startofpacket[] | In | [NUM_CHANNELS] | Assert this signal to indicate the beginning of the TX data. |
| avalon_st_tx_endofpacket[] | In | [NUM_CHANNELS] | Assert this signal to indicate the end of the TX data. |
| avalon_st_tx_valid[] | In | [NUM_CHANNELS] | Assert this signal to indicate that avalon_st_tx_data[] and other signals on this interface are valid. |
| avalon_st_tx_ready[] | Out | [NUM_CHANNELS] | When asserted, indicates that the MAC IP core is ready to accept data. The reset value of this signal is non-deterministic. |
| avalon_st_tx_error[] | In | [NUM_CHANNELS] | Assert this signal to indicate that the current TX packet contains errors. |
| avalon_st_tx_data[][] | In | [NUM_CHANNELS][m] |
TX data from the client. m is 64 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 32. |
| avalon_st_tx_empty[][] | In | [NUM_CHANNELS][m] |
Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data. m is 3 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 2.
|
| avalon_st_rx_startofpacket[] | Out | [NUM_CHANNELS] | When asserted, indicates the beginning of the RX data. |
| avalon_st_rx_endofpacket[] | Out | [NUM_CHANNELS] | When asserted, indicates the end of the RX data. |
| avalon_st_rx_valid[] | Out | [NUM_CHANNELS] | When asserted, indicates that the avalon_st_rx_ data[] signal and other signals on this interface are valid. |
| avalon_st_rx_ready[] | In | [NUM_CHANNELS] | Assert this signal when the client is ready to accept data. |
| avalon_st_rx_error[][] | Out | [NUM_CHANNELS][6] | When set to 1, the respective bits
indicate an error type:
|
| avalon_st_rx_data[][] | Out | [NUM_CHANNELS][m] |
RX data to the client. m is 64 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 32. |
| avalon_st_rx_empty[][] | Out | [NUM_CHANNELS][m] |
Contains the number of empty bytes during the cycle that contain the end of the RX data. m is 3 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 2. |
| avalon_st_tx_status_valid[] | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the avalon_st_txstatus_data[] and avalon_st_txstatus_error[] signals. |
| avalon_st_tx_status_data[][] | Out | [NUM_CHANNELS][40] | Contains information about the TX
frame.
|
| avalon_st_tx_status_error[][] | Out | [NUM_CHANNELS][7] | When set to 1, the respective bit
indicates the following error type in the RX frame.
|
| avalon_st_rxstatus_valid[] | Out | [NUM_CHANNELS] |
When asserted, this signal qualifies the avalon_st_rxstatus_data[] and avalon_st_rxstatus_error[] signals. The MAC IP core asserts this signal in the same clock cycle the avalon_st_rx_endofpacket signal is asserted. |
| avalon_st_rxstatus_data[][] | Out | [NUM_CHANNELS][40] | Contains information about the RX
frame.
|
| avalon_st_rxstatus_error[][] | Out | [NUM_CHANNELS][7] | When set to 1, the respective bit
indicates the following error type in the RX frame.
|
| avalon_st_pause_data[][] | In | [NUM_CHANNELS][2] | This signal takes effect when the
register bits, tx_pauseframe_enable[2:1], are both set to the default
value 0. Set this signal to the following values to trigger the corresponding actions.
|
8.4. PHY Interface Signals
| Signal | Direction | Description |
|---|---|---|
| rx_serial_data | In | RX serial input data |
| tx_serial_data | Out | TX serial output data |
8.5. Status Interface
| Signal | Direction | Description |
|---|---|---|
|
block_lock
|
Out | Asserted when the link synchronization is successful. |
|
led_an ethernet_1g_an |
Out | Asserted when auto-negotiation is completed. |
|
led_char_err ethernet_1g_char_err |
Out | Asserted when a 10-bit character error is detected in the RX data. |
|
led_disp_err ethernet_1g_disp_err |
Out | Asserted when a 10-bit running disparity error is detected in the RX data. |
|
channel_ready channel_tx_ready channel_rx_ready tx_ready_export rx_ready_export |
Out | Asserted when the channel is ready for data transmission. |
| atx_pll_locked | Out | Asserted when the TX PLL is locked. |
8.6. IEEE 1588v2 Timestamp Interface Signals
| Signal | Direction | Width | Description |
|---|---|---|---|
| tx_egress_timestamp_96b_valid[] | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the timestamp, tx_egress_timestamp_96b_data[], and the fingerprint, tx_egress_timestamp_96b_fingerprint[], of the TX frame. |
| tx_egress_timestamp_96b_data[][] | Out | [NUM_CHANNELS][96] | Carries the 96-bit egress timestamp in the
following format:
|
| tx_egress_timestamp_96b_fingerprint[][] | Out | [NUM_CHANNELS][TSTAMP_FP_WIDTH] |
Specifies the fingerprint of the TX frame that the 96-bit timestamp is for. |
| tx_egress_timestamp_64b_valid[] | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the timestamp, tx_egress_timestamp_64b_data[], and the fingerprint, tx_egress_timestamp_64b_fingerprint[], of the TX frame. |
| tx_egress_timestamp_64b_data[][] | Out | [NUM_CHANNELS][64] | Carries the 64-bit egress timestamp in the
following format:
|
| tx_egress_timestamp_64b_fingerprint[][] | Out | [NUM_CHANNELS][TSTAMP_FP_WIDTH] |
Specifies the fingerprint of the TX frame that the 64-bit timestamp is for. |
| rx_ingress_timestamp_96b_valid[] | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the timestamp, rx_ingress_timestamp_96b_data[]. The MAC IP core asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket. |
| rx_ingress_timestamp_96b_data[][] | Out | [NUM_CHANNELS][96] | Carries the 96-bit ingress timestamp in the
following format:
|
| rx_ingress_timestamp_64b_valid[] | Out | [NUM_CHANNELS] | When asserted, this signal qualifies the timestamp, rx_ingress_timestamp_64b_data[]. The MAC IP core asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket. |
| rx_ingress_timestamp_64b_data[][] | Out | [NUM_CHANNELS][64] | Carries the 64-bit ingress timestamp in the
following format:
|
8.7. Packet Classifier Interface Signals
| Signal | Direction | Width | Description |
|---|---|---|---|
| tx_egress_timestamp_request_in_valid[] | In | [NUM_CHANNELS] | Assert this signal to request timestamping for the TX frame. This signal must be asserted in the same clock cycle avalon_st_tx_startofpacket is asserted. |
| tx_egress_timestamp_request_in_fingerprint[][] | In | [NUM_CHANNELS][TSTAMP_FP_WIDTH] | Use this bus to specify the fingerprint that validates the timestamp for the incoming packet. |
| clock_operation_mode_mode[][] | In | [NUM_CHANNELS][2] | Use this signal to specify the clock mode.
|
| pkt_with_crc_mode[] | In | [NUM_CHANNELS] | Use this signal to specify whether or not a packet
contains CRC.
|
| tx_ingress_timestamp_valid[] | In | [NUM_CHANNELS] | Indicates whether or not the residence time can be
updated.
When this signal is deasserted, the tx_etstamp_ins_ctrl_out_residence_ti me_update signal also gets deasserted. |
| tx_ingress_timestamp_96b_data[][] | In | [NUM_CHANNELS][96] | 96-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet. |
| tx_ingress_timestamp_64b_data[][] | In | [NUM_CHANNELS][64] | 64-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet. |
| tx_ingress_timestamp_format[] | In | [NUM_CHANNELS] | The format of the timestamp for calculating the residence
time.
|
8.8. ToD Interface Signals
| Signal | Direction | Width | Description |
|---|---|---|---|
| master_pulse_per_second | Out | 1 | Pulse per second (PPS) from the master PPS module. The signal stay asserted for 10 ms. |
| start_tod_sync[] | In | [NUM_CHANNELS] | Use this signal to trigger the TOD synchronization process. The time of day of the local TOD is synchronized to the time of day of the master TOD. The synchronization process continues as long as this signal remains asserted. |
| pulse_per_second_10g[] | Out | [NUM_CHANNELS] | PPS from the 10G PPS module of channel n. The signal stay asserted for 10 ms. |
| pulse_per_second_1g[] | Out | [NUM_CHANNELS] | PPS from the 1G PPS module of channel n. The signal stay asserted for 10 ms. |
9. Configuration Registers Description
9.1. Register Access Definition
| Access | Definition |
|---|---|
| RO | Read only. |
| RW | Read and write. |
| RWC | Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP clears the bit(s) upon executing the instruction. |
9.2. Low Latency Ethernet 10G MAC
This topic lists the byte offsets the MAC registers.
| Byte Offset | R/W | Name | HW Reset |
|---|---|---|---|
| 0x2008 | RW | primary_mac_addr0 | 0x0 |
| 0x200C | RW | primary_mac_addr1 | 0x0 |
| Byte Offset | R/W | Name | HW Reset |
|---|---|---|---|
| 0x4000 | RW | tx_packet_control | 0x0 |
| 0x4004 | RO | tx_packet_status | 0x0 |
| 0x4100 | RW | tx_pad_control | 0x1 |
| 0x4200 | RW | tx_crc_control | 0x3 |
| 0x4400 | RW | tx_preamble_control | 0x0 |
| 0x6004 | RW | tx_frame_maxlength | 0x5EE(1518) |
| 0x4300 | RO | tx_underflow_counter0 | 0x0 |
| 0x4304 | RO | tx_underflow_counter1 | 0x0 |
| Byte Offset | R/W | Name | HW Reset |
|---|---|---|---|
| 0x4500 | RW | tx_pauseframe_control | 0x0 |
| 0x4504 | RW | tx_pauseframe_quanta | 0x0 |
| 0x4508 | RW | tx_pauseframe_enable | 0x1 |
| 0x4680 | RW | tx_pfc_priority_enable | 0x0 |
| 0x4600 | RW | pfc_pause_quanta_0 | 0x0 |
| 0x4604 | RW | pfc_pause_quanta_1 | 0x0 |
| 0x4608 | RW | pfc_pause_quanta_2 | 0x0 |
| 0x460C | RW | pfc_pause_quanta_3 | 0x0 |
| 0x4610 | RW | pfc_pause_quanta_4 | 0x0 |
| 0x4614 | RW | pfc_pause_quanta_5 | 0x0 |
| 0x4618 | RW | pfc_pause_quanta_6 | 0x0 |
| 0x461C | RW | pfc_pause_quanta_7 | 0x0 |
| 0x4640 | RW | pfc_holdoff_quanta_0 | 0x1 |
| 0x4644 | RW | pfc_holdoff_quanta_1 | 0x1 |
| 0x4648 | RW | pfc_holdoff_quanta_2 | 0x1 |
| 0x464C | RW | pfc_holdoff_quanta_3 | 0x1 |
| 0x4650 | RW | pfc_holdoff_quanta_4 | 0x1 |
| 0x4654 | RW | pfc_holdoff_quanta_5 | 0x1 |
| 0x4658 | RW | pfc_holdoff_quanta_6 | 0x1 |
| 0x465C | RW | pfc_holdoff_quanta_7 | 0x1 |
| Byte Offset | R/W | Name | HW Reset |
|---|---|---|---|
| 0x0000 | RW | rx_transfer_control | 0x0 |
| 0x0004 | RO | rx_transfer_status | 0x0 |
| 0x0100 | RW | rx_padcrc_control | 0x1 |
| 0x0200 | RW | rx_crccheck_control | 0x2 |
| 0x0400 | RW | rx_custom_preamble_forward | 0x0 |
| 0x0500 | RW | rx_preamble_control | 0x0 |
| 0x2000 | RW | rx_frame_control | 0x3 |
| 0x2004 | RW | rx_frame_maxlength | 1518 |
| 0x2010 | RW | rx_frame_spaddr0_0 | 0x0 |
| 0x2014 | RW | rx_frame_spaddr0_1 | 0x0 |
| 0x2018 | RW | rx_frame_spaddr1_0 | 0x0 |
| 0x201C | RW | rx_frame_spaddr1_1 | 0x0 |
| 0x2020 | RW | rx_frame_spaddr2_0 | 0x0 |
| 0x2024 | RW | rx_frame_spaddr2_1 | 0x0 |
| 0x2028 | RW | rx_frame_spaddr3_0 | 0x0 |
| 0x202C | RW | rx_frame_spaddr3_1 | 0x0 |
| 0x2060 | RW | rx_pfc_control | 0x1 |
| 0x0300 | RO | rx_pktovrflow_error | 0x0 |
| Byte Offset | R/W | Name | HW Reset |
|---|---|---|---|
| 0x4440 | RW | tx_period_10G | 0x33333 |
| 0x4448 | RW | tx_fns_adjustment_10G | 0x0 |
| 0x444C | RW | tx_ns_adjustment_10G | 0x0 |
| 0x4460 | RW | tx_period_mult_speed | 0x80000 |
| 0x4468 | RW | tx_fns_adjustment_mult_speed | 0x0 |
| 0x446C | RW | tx_ns_adjustment_mult_speed | 0x0 |
| Byte Offset | R/W | Name | HW Reset |
|---|---|---|---|
| 0x0440 | RW | rx_period_10G | 0x33333 |
| 0x0448 | RW | rx_fns_adjustment_10G | 0x0 |
| 0x044C | RW | rx_ns_adjustment_10G | 0x0 |
| 0x0460 | RW | rx_period_mult_speed | 0x80000 |
| 0x0468 | RW | rx_fns_adjustment_mult_speed | 0x0 |
| 0x046C | RW | rx_ns_adjustment_mult_speed | 0x0 |
| Byte Offset | R/W | Name | HW Reset |
|---|---|---|---|
| 0x7000 | RO | tx_stats_clr | 0x0 |
| 0x3000 | RO | rx_stats_clr | 0x0 |
| 0x7008:0x700C | RO | tx_stats_framesOK | 0x0 |
| 0x3008:0x300C | RO | rx_stats_framesOK | 0x0 |
| 0x7010:0x7014 | RO | tx_stats_framesErr | 0x0 |
| 0x3010:0x3014 | RO | rx_stats_framesErr | 0x0 |
| 0x7018:0x701C | RO | tx_stats_framesCRCErr | 0x0 |
| 0x3018:0x301C | RO | rx_stats_framesCRCErr | 0x0 |
| 0x7020:0x7024 | RO | tx_stats_octetsOK | 0x0 |
| 0x3020:0x3024 | RO | rx_stats_octetsOK | 0x0 |
| 0x7028:0x702C | RO | tx_stats_pauseMACCtrl_Frames | 0x0 |
| 0x3028:0x302C | RO | rx_stats_pauseMACCtrl_Frames | 0x0 |
| 0x7030:0x7034 | RO | tx_stats_ifErrors | 0x0 |
| 0x3030:0x3034 | RO | rx_stats_ifErrors | 0x0 |
| 0x7038:0x703C | RO | tx_stats_unicast_FramesOK | 0x0 |
| 0x3038:0x303C | RO | rx_stats_unicast_FramesOK | 0x0 |
| 0x7040:0x7044 | RO | tx_stats_unicast_FramesErr | 0x0 |
| 0x3040:0x3044 | RO | rx_stats_unicast_FramesErr | 0x0 |
| 0x7048:0x704C | RO | tx_stats_multicast_FramesOK | 0x0 |
| 0x3048:0x304C | RO | rx_stats_multicast_FramesOK | 0x0 |
| 0x7050:0x7054 | RO | tx_stats_multicast_FramesErr | 0x0 |
| 0x3050:0x3054 | RO | rx_stats_multicast_FramesErr | 0x0 |
| 0x7058:0x705C | RO | tx_stats_broadcast_FramesOK | 0x0 |
| 0x3058:0x305C | RO | rx_stats_broadcast_FramesOK | 0x0 |
| 0x7060:0x7064 | RO | tx_stats_broadcast_FramesErr | 0x0 |
| 0x3060:0x3064 | RO | rx_stats_broadcast_FramesErr | 0x0 |
| 0x7068:0x706C | RO | tx_stats_etherStatsOctets | 0x0 |
| 0x3068:0x306C | RO | rx_stats_etherStatsOctets | 0x0 |
| 0x7070:0x7074 | RO | tx_stats_etherStatsPkts | 0x0 |
| 0x3070:0x3074 | RO | rx_stats_etherStatsPkts | 0x0 |
| 0x7078:0x707C | RO | tx_stats_etherStatsUndersizePkts | 0x0 |
| 0x3078:0x307C | RO | rx_stats_etherStatsUndersizePkts | 0x0 |
| 0x7080:0x7084 | RO | tx_stats_etherStatsOversizePkts | 0x0 |
| 0x3080:0x3084 | RO | rx_stats_etherStatsOversizePkts | 0x0 |
| 0x7088:0x708C | RO | tx_stats_etherStatsPkts64Octets | 0x0 |
| 0x3088:0x308C | RO | rx_stats_etherStatsPkts64Octets | 0x0 |
| 0x7090:0x7094 | RO | tx_stats_etherStatsPkts65to127Octets | 0x0 |
| 0x3090:0x3094 | RO | rx_stats_etherStatsPkts65to127Octets | 0x0 |
| 0x7098:0x709C | RO | tx_stats_etherStatsPkts128to255Octets | 0x0 |
| 0x3098:0x309C | RO | rx_stats_etherStatsPkts128to255Octets | 0x0 |
| 0x70A0:0x70A4 | RO | tx_stats_etherStatsPkts256to511Octets | 0x0 |
| 0x30A0:0x30A4 | RO | rx_stats_etherStatsPkts256to511Octets | 0x0 |
| 0x70A8:0x70AC | RO | tx_stats_etherStatsPkts512to1023Octets | 0x0 |
| 0x30A8:0x30AC | RO | rx_stats_etherStatsPkts512to1023Octets | 0x0 |
| 0x70B0:0x70B4 | RO | tx_stats_etherStatPkts1024to1518Octets | 0x0 |
| 0x30B0:0x30B4 | RO | rx_stats_etherStatPkts1024to1518Octets | 0x0 |
| 0x70B8:0x70BC | RO | tx_stats_etherStatsPkts1519toXOctets | 0x0 |
| 0x30B8:0x30BC | RO | rx_stats_etherStatsPkts1519toXOctets | 0x0 |
| 0x70C0:0x70C4 | RO | tx_stats_etherStatsFragments | 0x0 |
| 0x30C0:0x30C4 | RO | rx_stats_etherStatsFragments | 0x0 |
| 0x70C8:0x70CC | RO | tx_stats_etherStatsJabbers | 0x0 |
| 0x30C8:0x30CC | RO | rx_stats_etherStatsJabbers | 0x0 |
| 0x70D0:0x70D4 | RO | tx_stats_etherStatsCRCErr | 0x0 |
| 0x30D0:0x30D4 | RO | rx_stats_etherStatsCRCErr | 0x0 |
| 0x70D8:0x70DC | RO | tx_stats_unicastMACCtrlFrames | 0x0 |
| 0x30D8:0x30DC | RO | rx_stats_unicastMACCtrlFrames | 0x0 |
| 0x70E0:0x70E4 | RO | tx_stats_multicastMACCtrlFrames | 0x0 |
| 0x30E0:0x30E4 | RO | rx_stats_multicastMACCtrlFrames | 0x0 |
| 0x70E8:0x70EC | RO | tx_stats_broadcastMACCtrlFrames | 0x0 |
| 0x30E8:0x30EC | RO | rx_stats_broadcastMACCtrlFrames | 0x0 |
| 0x70F0:0x70F4 | RO | tx_stats_PFCMACCtrlFrames | 0x0 |
| 0x30F0:0x30F4 | RO | rx_stats_PFCMACCtrlFrames | 0x0 |
9.3. PHY
9.3.1. 1G/10G PHY
This topic lists the byte offsets of the 1G/10G variant registers for Intel® Arria® 10 devices.
| Byte Offset | Bit | R/W | Name |
|---|---|---|---|
| 0x1110 | 1 | RW | reset_tx_digital |
| 2 | RW | reset_rx_analog | |
| 3 | RW | reset_rx_dgital | |
| 0x1184 | 0 | RW | phy_serial_loopback |
| 0x1190 | 0 | RW | pma_rx_set_locktodata |
| 0x1194 | 0 | RW | pma_rx_set_locktoref |
| 0x1198 | 0 | RO | pma_rx_is_lockedtodata |
| 0x119C | 0 | RO | pma_rx_is_lockedtoref |
| 0x12A0 | 0 | RW | tx_invpolarity |
| 1 | RW | rx_invpolarity | |
| 2 | RW | rx_bitreversal_enable | |
| 3 | RW | rx_bytereversal_enable | |
| 4 | RW | force_electrical_idle | |
| 0x12A4 | 0 | R | rx_syncstatus |
| 1 | R | rx_patterndetect | |
| 2 | R | rx_rlv | |
| 3 | R | rx_rmfifodatainserted | |
| 4 | R | rx_rmfifodatadeleted | |
| 5 | R | rx_disperr | |
| 6 | R | rx_errdetect |
| Byte Offset | Bit | R/W | Name |
|---|---|---|---|
| 0x1200 | RW | Indirect_addr | |
| 0x1204 | 2 | RW | RCLR_ERRBLK_CNT |
| 3 | RW | RCLR_BER_COUNT | |
| 0x1208 | 1 | RO | HI_BER |
| 2 | RO | BLOCK_LOCK | |
| 3 | RO | TX_FULL | |
| 4 | RO | RX_FULL | |
| 7 | RO | Rx_DATA_READY |
| Byte Offset | Bit | R/W | Name |
|---|---|---|---|
| 0x1240 | 9 | RW | RESTART_AUTO_NEGOTIATION |
| 12 | RW | AUTO_NEGOTIATION_ENABLE | |
| 15 | RW | RESET | |
| 0x1244 | 2 | R | LINK_STATUS |
| 3 | R | AUTO_NEGOTIATION_ ABILITY | |
| 5 | R | AUTO_NEGOTIATION_ COMPLETE | |
| 0x1250 | 5 | RW | FD |
| 6 | RW | HD | |
| 8:7 | RW | PS2,PS1 | |
| 13:12 | RW | RF2,RF1 | |
| 14 | R0 | ACK | |
| 15 | RW | NP | |
| 0x1254 | 5 | R | FD |
| 6 | R | HD | |
| 8:7 | R | PS2,PS1 | |
| 13:12 | R | RF2,RF1 | |
| 14 | R | ACK | |
| 15 | R | NP | |
| 0x1258 | 0 | R | LINK_PARTNER_AUTO_NEGOTIATION_ABLE |
| 1 | R | PAGE_RECEIVE | |
| 0x1288 | 15:0 | RW | AN link timer[15:0] |
| 0x128C | 4:0 | RW | AN link timer[4:0] |
| 0x1290 | 0 | RW | SGMII_ENA |
| 1 | RW | USE_SGMII_AN | |
| 3:2 | RW | SGMII_SPEED |
9.3.2. 1G/2.5G/5G/10G Multi-rate PHY
This topic lists the byte offsets of the 1G/2.5G/5G/10G Multi-rate variant registers for Intel® Arria® 10 devices.
Register Map
You can access the 16-bit/32-bit configuration registers via the Avalon® memory-mapped interface.
| Address Range | Usage | Register Width | Configuration |
|---|---|---|---|
| 0x00 : 0x1F | 1000BASE-X/SGMII | 16 | 2.5G, 1G/2.5G, 1G/2.5G/10G |
| 0x400 : 0x41F | USXGMII | 32 | 1G/2.5G/5G/10G (USXGMII) |
| 0x461 | Serial Loopback | 32 | 1G/2.5G/5G/10G (USXGMII) |
Register Definitions
- Do not write to reserved or undefined registers.
- When writing to the registers, perform read-modify-write operation to ensure that reserved or undefined register bits are not overwritten.
| Word Offset | Name | Description | Access | HW Reset Value |
|---|---|---|---|---|
| 0x00 | control | Bit [15]: RESET. Set this bit to 1 to trigger a soft reset. The PHY clears the bit when the reset is completed. The register values remain intact during the reset. |
RWC | 0 |
| Bit[14]: LOOPBACK. Set this bit to 1 to enable loopback on the serial interface. | RW | 0 | ||
| Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bit to 1 to enable auto-negotiation. Auto-negotiation is supported only in 1GbE. Therefore, set this bit to 0 when you switch to a speed other than 1GbE. |
RW | 0 | ||
| Bit [9]: RESTART_AUTO_NEGOTIATION. Set this bit to 1 to restart auto-negotiation. The PHY clears the bit as soon as auto-negotiation is restarted. |
RWC | 0 | ||
| All other bits are reserved. | — | — | ||
| 0x01 | status | Bit [5]: AUTO_NEGOTIATION_COMPLETE. A value of "1" indicates that the auto-negotiation is completed. | RO | 0 |
| Bit [3]: AUTO_NEGOTIATION_ABILITY. A value of "1" indicates that the PCS function supports auto-negotiation. | RO | 1 | ||
| Bit [2]: LINK_STATUS. A value of "0" indicates that the link is lost. A value of "1" indicates that the link is established. | RO | 0 | ||
| All other bits are reserved. | — | — | ||
| 0x02:0x03 | phy_identifier | The value set in the PHY_IDENTIFIER parameter. | RO | Value of PHY_IDENTIFIER parameter |
| 0x04 | dev_ability | Use this register to advertise the device abilities during auto-negotiation. | — | — |
Bits [13:12]: RF. Specify the remote fault.
|
RW | 00 | ||
Bits [8:7]: PS. Specify the PAUSE support.
|
RW | 11 | ||
| Bit [5]: FD. Ensure that this bit is always set to 1. | RW | 1 | ||
| All other bits are reserved. | — | — | ||
| 0x05 (1000BASE-X mode) | partner_ability | The device abilities of the link partner during auto-negotiation. | — | — |
| Bit [14]: ACK. A value of "1" indicates that the link partner has received three consecutive matching ability values from the device. | RO | 0 | ||
Bits [13:12]: RF. The remote fault.
|
RO | 0 | ||
Bits [8:7]: PS. The PAUSE support.
|
RO | 0 | ||
| Bit [6]: HD. A value of "1" indicates that half-duplex is supported. | RO | 0 | ||
| Bit [5]: FD. A value of "1" indicates that full-duplex is supported. | RO | 0 | ||
| All other bits are reserved. | — | — | ||
| 0x05 (SGMII mode) | partner_ability | The device abilities of the link partner during auto-negotiation. | — | — |
| Bit [11:10]: COPPER_SPEED
Link partner speed:
|
RO | 00 | ||
| Bit [12]: COPPER_DUPLEX_STATUS
Link partner capability:
|
RO | 0 | ||
| Bit [14]: ACK. Link partner acknowledge. A value of 1 indicates that the device received three consecutive matching ability values from its link partner. | RO | 0 | ||
| Bit [15]: COPPER_LINK_STATUS
Link partner status:
|
RO | 0 | ||
| All other bits are reserved. | — | — | ||
| 0x06 | an_expansion | The PCS capabilities and auto-negotiation status. | — | — |
| Bit [1]: PAGE_RECEIVE. A value of "1" indicates that the partner_ability register has been updated. This bit is automatically cleared once it is read. | RO | 0 | ||
| Bit [0]: LINK_PARTNER_AUTO_NEGOTIATION_ABLE. A value of "1" indicates that the link partner supports auto-negotiation. | RO | 0 | ||
| 0x07 | device_next_page | The PHY does not support the next page feature. These registers are always set to 0. | RO | 0 |
| 0x08 | partner_next_page | RO | 0 | |
| 0x09:0x0F | Reserved | — | — | — |
|
0x10 |
scratch | Provides a memory location to test read and write operations. |
RW |
0 |
| Bit [31:16]: Reserved | — | — | ||
| 0x11 | rev | The current version of the PHY IP. | RO | Current version of the PHY |
| Bit [31:16]: Reserved | — | — | ||
| 0x12:0x13 | link_timer | 21-bit auto-negotiation link timer.
|
RW | 0 |
| 0x14 | if_mode | Interface Mode Register | — | — |
| Bit [0]: SGMII_ENA
Determines the PCS function operating mode. Setting this bit to 1b'1 enables SGMII mode. Setting this bit to 1b'0 enables 1000BASE-X gigabit mode. |
RW | 0 | ||
| Bit [1]: USE_SGMII_AN
In SGMII mode, setting this bit to 1b'1 configures the PCS with the link partner abilities advertised during auto-negotiation. If this bit is set to 1b'0, the PCS function should be configured with the SGMII_SPEED bits. |
RW | 0 | ||
| Bit [3:2]: SGMII_SPEED
When the PCS operates in SGMII mode (SGMII_ENA = 1) and is not programmed for automatic configuration (USE_SGMII_AN = 0), the following encodings specify the speed:
|
RW | 0 | ||
| All other bits are reserved. | — | — | ||
| 0x15:0x1F | Reserved | — | — | — |
| 0x400 | usxgmii_control | Control Register | — | — |
Bit [0]: USXGMII_ENA:
|
RW | 0 | ||
Bit [1]: USXGMII_AN_ENA is used when USXGMII_ENA is set to 1:
|
RW | 1 | ||
Bit [4:2]: USXGMII_SPEED is the operating speed of the PHY in USXGMII mode and USE_USXGMII_AN is set to 0.
|
RW | 0 | ||
| Bit [8:5]: Reserved | — | — | ||
| Bit [9]: RESTART_AUTO_NEGOTIATION Write 1 to restart Auto-Negotiation sequence The bit is cleared by hardware when Auto-Negotiation is restarted. |
RWC | 0 | ||
| Bit [31:10]: Reserved | — | — | ||
| 0x401 | usxgmii_status | Status Register | — | — |
| Bit [1:0]: Reserved | — | — | ||
Bit [2]: LINK_STATUS indicates link status for USXGMII all speeds
|
RO | 0 | ||
| Bit [4:3]: Reserved | — | — | ||
| Bit [5]: AUTO_NEGOTIATION_COMPLETE
A value of 1 indicates the Auto-Negotiation process is completed. |
RO | 0 | ||
| Bit [31:6]: Reserved | — | — | ||
| 0x402:0x404 | Reserved | — | — | — |
| 0x405 | usxgmii_partner_ability | Device abilities advertised to the link partner during Auto-Negotiation | — | — |
| Bit [6:0]: Reserved | — | — | ||
| Bit [7]: EEE_CLOCK_STOP_CAPABILITY
Indicates whether or not energy efficient Ethernet (EEE) clock stop is supported.
|
RO | 0 | ||
| Bit [8]: EEE_CAPABILITY
Indicates whether or not EEE is supported.
|
RO | 0 | ||
Bit [11:9]: SPEED
|
RO | 0 | ||
| Bit [12]: DUPLEX
Indicates the duplex mode.
|
RO | 0 | ||
| Bit [13]: Reserved | — | — | ||
| Bit [14]: ACKNOWLEDGE
A value of 1 indicates that the device has received three consecutive matching ability values from its link partner. |
RO | 0 | ||
| Bit [15]: LINK
Indicates the link status.
|
RO | 0 | ||
| Bit [31:16]: Reserved | — | — | ||
| 0x406:0x411 | Reserved | — | — | — |
| 0x412 | usxgmii_link_timer |
Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T PHY IP. The reset value sets the link timer to approximately 1.6 ms. Bits [13:0] are reserved and always set to 0. |
[19:14]: RW [13:0]: RO |
[19:14]: 1F [13:0]: 0 |
| 0x413:0x41F | Reserved | — | — | — |
| 0x461 | phy_serial_loopback | Configures the transceiver serial loopback in the PMA from TX to RX. | — | — |
Bit [0]
|
RW | 0 | ||
| Bit [31:1]: Reserved | — | — |
9.4. Transceiver Reconfiguration
| Word Offset | Name | Bits | Description | Access | HW Reset |
|---|---|---|---|---|---|
| 0x00 | logical_channel_number | [9:0] | The logical number of the reconfiguration block. | RW | 0x000 |
| [31:10] | Reserved | — | — | ||
| 0x01 | control | [1:0] | Specify the new
operating speed:
|
RW | 0x00 |
| [15:2] | Reserved | — | 0x000 | ||
| [16] |
Writing 1 to this bit when it is 0 starts the reconfiguration process. The bit clears when the process is completed. |
RWC | 0x0 | ||
| [31:17] | Reserved | — | 0x000000 | ||
| 0x02 | status | [0] | When set to 1, indicates the reconfiguration process is in progress. | RO | 0x0 |
| [31:1] | Reserved | — | — |
9.5. TOD
| Byte Offset | Name | Bits | Description | Access | HW Reset |
|---|---|---|---|---|---|
| 0x0000 | SecondsH | [15:0] | The upper 16 bits of the second field. | RW | 0x0 |
| [31:16] | Reserved. | — | — | ||
| 0x0004 | SecondsL | 32 | The lower 32 bits of the second field. | RW | 0x0 |
| 0x0008 | NanoSec | 30 | The nanosecond field. | RW | 0x0 |
| 0x0010 | Period | [15:0] | The time of day. The period in fractional nanosecond. | RW | n 4 |
| [19:16] | The time of day. The period in nanosecond. | ||||
| [31:20] | Reserved. | — | — | ||
| 0x0014 | AdjustPeriod | [15:0] | The offset adjustment period. The period in fractional nanosecond. | RW | 0x0 |
| [19:16] | The offset adjustment period. The period in nanosecond. | ||||
| [31:20] | Reserved. | — | — | ||
| 0x0018 | AdjustCount | [19:0] | The number of adjusted period in clock cycles. | RW | 0x0 |
| [31:20] | Not used. | — | — |
10. Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide Archives
| Intel® Quartus® Prime Version | IP Core Version | User Guide |
|---|---|---|
| 18.0 | 18.0 | Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide |
| 17.1 | 17.1 | Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel® Arria® 10 Devices |
| 16.1 | 16.1 | Low Latency Ethernet 10G MAC Design Example User Guide |
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide
| Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
|---|---|---|---|
| 2020.11.30 | 19.1 | 19.1 |
|
| 2019.09.23 | 19.1 | 19.1 |
|
| 2019.05.10 | 19.1 | 19.1 |
|
| 2019.04.15 | 19.1 | 19.1 |
|
| 2018.10.05 | 18.0 | 18.0 |
|
| 2018.05.16 | 18.0 | 18.0 |
|
| 2018.03.28 | 17.1 | 17.1 |
|
| Date | Version | Changes |
|---|---|---|
| November 2017 | 2017.11.13 |
|
| 2017.11.06 |
|
|
| June 2017 | 2017.06.20 | Corrected typographical errors in the Design Components topic for 1G/2.5G Ethernet design example. |
| 2017.06.19 |
|
|
| October 2016 | 2016.10.31 |
|
| May 2016 | 2016.05.20 |
|
| December 2015 | 2015.12.14 | Initial release. |