Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide

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UG-20016 | 2018.05.16

Quick Start Guide

The Intel^® FPGA Low Latency 10G Ethernet (LL 10GbE) MAC Intel^® FPGA IP core for Intel^® Arria^® 10 devices provides the capability of generating design examples for selected configurations.

Figure 1. Development Stages for the Design Example

Directory Structure

Figure 2. Directory Structure for the Design Example

Table 1. Directory and File Description
Directory/File	Description
altera_eth_top.qpf	Intel^® Quartus^® Prime project file.
altera_eth_top.qsf	Intel^® Quartus^® Prime settings file.
altera_eth_top.sv	Design example top-level HDL.
altera_eth_top.sdc	Synopsys Design Constraints (SDC) file.
rtl	The folder that contains the design example synthesizable components.
rtl/altera_eth_10g_mac_base_r.sv rtl/altera_10g_mac_base_r_wrap.v	Design example DUT top-level files for 10GBASE-R Ethernet design example.
rtl/altera_mge_rd.sv rtl/altera_mge_channel.v	Design example DUT top-level files for the following Ethernet design examples: 1G/2.5G with 1588v2 feature 1G/2.5G/10G
rtl/altera_eth_channel.v rtl/altera_eth_multi_channel.sv	Design example DUT top-level files for the following Ethernet design examples: 10M/100M/1G/10G 1G/10G
rtl/altera_eth_channel_1588.v rtl/altera_eth_multi_channel_1588.sv	Design example DUT top-level files for the following Ethernet design examples: 10M/100M/1G/10G with with 1588v2 feature 1G/10G with 1588v2 feature
rtl/altera_mge_multi_channel.sv rtl/altera_mge_channel.v	Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example.
rtl/<Design Component>	The folder for each synthesizable component including Platform Designer generated IPs, such as LL 10GbE MAC, PHY, and FIFO.
simulation/ed_sim/models	The folder that contains the testbench files.
simulation/ed_sim/cadence simulation/ed_sim/mentor simulation/ed_sim/synopsys/vcs simulation/ed_sim/xcelium	The folder that contains the simulation script. It also serves as a working area for the simulator.
hwtesting/system_console	The folder that contains system console scripts for hardware testing.
output_files	The folder that contains Intel^® Quartus^® Prime output files including Intel^® Quartus^® Prime compilation reports and design programing file (.sof file).

Generating the Design

Procedure

You can generate the design example from the IP Parameter Editor.

Figure 3. Example Design Tab

Select Tools > IP Catalog to open the IP Catalog and select Low Latency Ethernet 10G MAC Intel^® FPGA IP .
The IP parameter editor appears.
Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK.
To generate a design example, select a design example preset from the Presets library and click Apply. When you select a design, the system automatically populates the IP parameters for the design.
The Parameter Editor automatically sets the parameters required to generate the design example. Do not change the preset parameters in the IP tab.
Specify the parameters in the Example Design tab.
Click the Generate Example Design button.

The software generates all design files in sub-directories. You require these files to run simulation, compilation, and hardware testing.

Design Example Parameters

Table 2. Parameters in the Example Design Tab
Parameter	Description
Select Design	Available example designs for the IP parameter settings. When you select an example design from the Preset library, this field shows the selected design.
Example Design Files for Simulation or Synthesis	The files to generate for the different development phase. Simulation—generates the necessary files for simulating the example design. Synthesis—generates the synthesis files. Use these files to compile the design in the Intel^® Quartus^® Prime software for hardware testing and perform static timing analysis.
Generate File Format	The format of the RTL files for simulation—Verilog or VHDL.
Select Board	Supported hardware for design implementation. When you select an Intel FPGA development board, the `Target Device` is the one that matches the device on the Development Kit. If this menu is grayed out, there is no supported board for the options that you select. Intel^® Arria^® 10 GX Transceiver Signal Integrity Development Kit : This option allows you to test the design example on selected Intel FPGA IP development kit. This selection automatically selects the `Target Device` to match the device on the Intel^® FPGA IP development kit. If your board revision has a different device grade, you can change the target device. Custom Development Kit: This option allows you to test the design example on a third party development kit with Intel^® FPGA IP device, a custom designed board with Intel^® FPGA IP device, or a standard Intel^® FPGA IP development kit not available for selection. You can also select a custom device for the custom development kit. No Development Kit: This option excludes the hardware aspects for the design example.
Change Target Device	Select this parameter to display and select all devices for the Intel^® FPGA IP development kit.
Specify Number of Channels	The number of Ethernet channels.
Enable ADME support	Turn on this option to enable Transceiver ADME feature.
Partial Reconfiguration Ready	When this option is enabled, the generated hierarchy of the design example is compliance with the partial reconfiguration flow, where there is clear separation between hard IP and soft IP, without any functionality changes. Hard IPs such as Native PHY, JTAG, transmitter PLL, and FPLL are instantiated at the top-level wrapper of design example.

Compiling and Simulating the Design

Procedure

You can compile and simulate the design by running a simulation script from the command prompt.

At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator> .

Run the simulation script for the simulator of your choice.

Simulator	Working Directory	Command
ModelSim^®	`<Example Design>`/simulation/ed_sim/mentor	`vsim -c -do tb_run.tcl`
VCS^®	`<Example Design>`/simulation/ed_sim/synopsys/vcs	`sh tb_run.sh`
NCSim	`<Example Design>`/simulation/ed_sim/cadence	`sh tb_run.sh`
Xcelium™	`<Example Design>`/simulation/ed_sim/xcelium	`sh tb_run.sh`

A successful simulation ends with the following message:

Simulation stopped due to successful completion! Simulation passed.

After successful completion, you can analyze the results.

Testbench

Figure 4. Block Diagram of the Testbench

Table 3. Testbench Components
Component	Description
Device under test (DUT)	The design example.
Avalon driver	Consists of Avalon-ST master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon-MM interface of the DUT.
Ethernet packet monitors	Monitor TX and RX datapaths, and display the frames in the simulator console.

Compiling and Testing the Design in Hardware

Procedure

You can compile and test the design in the supported Intel FPGA development kit.

Launch the Intel^® Quartus^® Prime software and open the design example project file. Select Processing > Start Compilation to compile the design example.
The timing constraints for the design example and the design components are automatically loaded during compilation.
Connect the development board to the host computer.
Launch the Clock Control application, which is part of the development kit, and set new frequencies for the design example.

Note: For the frequencies to set, refer to the Hardware Testing section in the respective design example chapter.
In the Intel^® Quartus^® Prime software, select Tools > Programmer to configure the FPGA on the development board using the generated .sof file.
Reset the system by pressing the PB0 push button.
In the Intel^® Quartus^® Prime software, select Tools > System Debugging Tools > System Console to launch the system console.
Change the working directory to <Example Design>\hwtesting\system_console.
Initialize the design command list by running this command: source main.tcl.

Note: For a design example that does not provide the main.tcl file, refer to the Hardware Testing section in the respective design example chapter.

You can now run any of the predefined hardware tests from the System Console.

Observe the test results displayed.

Hardware Setup

Figure 5. Block Diagram of the Hardware Setup

10M/100M/1G/10G Ethernet Design Example for Intel Arria 10 Devices

The 10M/100M/10G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel^® FPGA IP core operating at various speeds.

Generate the design example from the Example Design tab of the LL 10GbE Intel^® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature.

Features

Multi-speed Ethernet operation—10M, 100M, 1G, and 10G.
Support for up to 12 channels.
Packet monitoring on the TX and RX datapaths.
Option to generate the design example with the IEEE 1588v2 feature.
Tested with the Spirent TestCenter.

Functional Description

The design examples consist of various components. The following block diagrams show the design components and the top-level signals of the design examples.

Figure 6. Block Diagram—10M/100M/1G/10G Ethernet Design Example without IEEE 1588v2 Feature

Figure 7. Block Diagram—10M/100M/1G/10G Ethernet Design Example with IEEE 1588v2 Feature

Design Components

Table 4. Design Components
Component	Description
LL 10GbE MAC	The Low Latency Ethernet 10G MAC Intel^® FPGA IP core with the following configuration: Speed: 10M/100M/1G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the design example with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY	The 1G/10G and 10GBASE-KR PHY Intel^® Arria^® 10 FPGA IP. The design example uses the 1G/10G IP variant.
Address decoder	Decodes the addresses of the components in each Ethernet channel.
Multi-channel address decoder	Decodes the addresses of the components used by all channels, such as the Master TOD module.
Reset controller	Synchronizes the reset of all design components.
Transceiver Reset Controller	The Transceiver PHY Reset Controller Intel^® FPGA IP core. Resets the transceiver.
PLL	Generates clocks for all design components.
ATX PLL	Generates a TX serial clock for the Intel^® Arria^® 10 10G transceiver.
fPLL	Generates a TX serial clock for the Intel^® Arria^® 10 1G transceiver.
MDIO	Provides an MDIO interface to the external PHY.
FIFO	The Avalon^® Streaming ( Avalon^® -ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client. The default depth is 512. To increase the depth of the FIFO, change the `DC_FIFO_DEPTH` and `SC_FIFO_DEPTH` parameter values from 512 to 2048, under `altera_eth_fifo` instance in <Example Design>/rtl/altera_eth_channel.sv.
Design Components for the IEEE 1588v2 Feature
Master TOD	The master TOD for all channels.
TOD Sync	Synchronizes the Master TOD to all Local TODs.
Local TOD	The TOD for each channel.
Master Pulse Per Second	Returns pulse per second (pps) for all channels.
Pulse Per Second	Returns pulse per second (pps) for each channel.
PTP packet classifier	Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel^® FPGA IP core.

Simulation

The simulation test cases demonstrate how the channel speed and the configuration of the PHY are changed. These test cases use circular loopback on the total number of Ethernet channels. The following table describes the steps to change the speed and configuration.

Table 5. Ethernet Operations
Operation	Description
Configuring the PHY speed.	Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), 1G1000Base-X or 1G/100M/10M SGMII.
Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X.	Write one of the following values to the PHY's register at address offset 0x12C0. 0x01: Turn on the auto-detection mode. In this mode, the PHY automatically detects the speed. 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps. 0x41: Turn off the auto-detection mode and set the speed to 10 Gbps. Example To set port 0 to 1000BASE-X: `write_32 0x02_52C0 0x11` To set port 0 to auto-detection mode: `write_32 0x02_52C0 0x01`
Changing the speed between 1 Gbps, 100 Mbps, and 10 Mbps in SGMII.	Set the port to 1000BASE-X. Write one of the following values to the PHY's register at offset 0x1290. 0x01: Enable SGMII and set the speed to 10 Mbps. 0x03: Enable SGMII and auto-negotiation. 0x05: Enable SGMII mode and set the speed to 100 Mbps 0x09: Enable SGMII mode and set the speed to 1 Gbps Example: To set port 0 to SGMII and 100 Mbps: Set port 0 to 1000Base-X: `write_32 0x02_52C0 0x11` Set port 0 to 100-Mbps SGMII: `write_32 0x02_5290 0x05`

Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

In the Clock Control application, which is part of the development kit, set the following frequencies:

Y5—644.53125 MHz
Y6—125 MHz

Test Cases

You can run any of the following tests from the System Console.

Table 6. Hardware Test Cases
Test Case	Command	Example
PHY internal serial loopback	`TEST_PHYSERIAL_LOOPBACK` <channel> <speed_test> <burst_size>	`TEST_PHYSERIAL_LOOPBACK 0 10G 1000`
SMA loopback	For the design with the IEEE 1588v2 feature: `TEST_SMA_LB` <channel> <speed_test> <burst_size>	`TEST_SMA_LB 0 10G 1000`
SMA loopback	For the design without the IEEE 1588v2 feature: `TEST_SMA_LOOPBACK` <channel> <speed_test> <burst_size>	`TEST_SMA_LB 0 10G 1000`

Table 7. Command Parameters
Parameter	Valid Values	Description
`channel`	0 to the number of channel specified for the design	The number of channels for the test.
`speed_test`	10G, 1G, 100M, 10M	The PHY speed.
`burst_size`	—	The number of packets to generate for the test.

When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output.

Figure 14. Sample Test Output—Ethernet Packet Monitor

Figure 15. Sample Test Output—Statistics Counters

Signal Tap Debug Signals

The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below:

set_global_assignment -name ENABLE_SIGNALTAP ON

Table 8. Signal Tap Debug Signals
Component	Module Name	Signal
Top-level design example	`altera_eth_top`	`mm_clk` `ref_clk_1g` `ref_clk_10g` `channel_ready_n` `channel_reset_n` `master_reset_n`
Multi-channel wrapper	Design example without the IEEE 1588v2 feature: `altera_eth_top.altera_eth_multi_channel` Design example with the IEEE 1588v2 feature: `altera_eth_top.altera_eth_multi_channel_1588`	`pll_locked` `pll_1_locked` `pll_2_locked` (only for the design example with the IEEE 1588v2 feature) `pll_locked_10g` `pll_locked_1g`
MAC IP core	<n>`.altera_eth_10g_mac` ¹	`avalon_st_tx_startofpacket` `avalon_st_tx_endofpacket` `avalon_st_tx_data` `avalon_st_tx_ready` `avalon_st_tx_valid` `avalon_st_tx_error` `avalon_st_tx_empty` `avalon_st_rx_startofpacket` `avalon_st_rx_endofpacket` `avalon_st_rx_data` `avalon_st_rx_ready` `avalon_st_rx_valid` `avalon_st_rx_error` `avalon_st_rx_empty`
PHY	<n>`.altera_eth_10gkr_phy` ¹	`led_an` `led_char_err` `led_disp_err` `led_link` `mii_speed_sel` `rx_analogreset` `rx_block_lock` `rx_cal_busy` `rx_is_lockedtodata` `rx_digitalreset` `rx_data_ready` `tx_analogreset` `tx_digitalreset`
XGMII	<n>`.altera_eth_10g_mac.alt_em10g32.alt_em10g32unit` ¹	`xgmii_tx_control` `xgmii_tx_data` `xgmii_rx_control` `xgmii_rx_data` `link_fault_status_xgmii_rx_data`
GMII	<n>`.altera_eth_10g_mac` ¹	`gmii_tx_d` `gmii_tx_en` `gmii_tx_err` `gmii_rx_d` `gmii_rx_dv` `gmii_rx_err`
MII	<n>`.altera_eth_10g_mac` ¹	`mii_tx_d` `mii_tx_en` `mii_tx_err` `mii_rx_dv` `mii_rx_err`

¹ Replace n with:

altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design example without the IEEE 1588v2 feature.
altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588 for the design example with the IEEE 1588v2 feature.

Interface Signals

Figure 16. Interface Signals of the 10M/100M/1G/10G Ethernet Design Example

Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon-MM interface.

Table 9. Register Map
Byte Offset	Block
0x00_0000	Client logic
0x00_F000	Reserved
0x01_0000	Master TOD
Channel 0
0x02_0000	Reserved
0x02_4000	PHY
0x02_7800	10G TOD
0x02_7900	1G TOD
0x02_8000	LL 10GbE MAC
Channel 1
0x03_0000	Reserved
0x03_4000	PHY
0x03_7800	10G TOD
0x03_7900	1G TOD
0x03_8000	LL 10GbE MAC
.. and so forth up to Channel 11.
0x0E_0000 onwards	Client Logic

1G/10G Ethernet Design Example for Intel Arria 10 Devices

The 1G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel^® FPGA IP core operating at 1G and 10G.

Generate the design example from the Example Design tab of the LL 10GbE Intel^® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature.

Features

Dual-speed Ethernet operation—1G and 10G.
Support for up to 12 channels.
Packet monitoring on the TX and RX datapaths.
Option to generate the design example with the IEEE 1588v2 feature.
Tested with the Spirent TestCenter.

Hardware and Software Requirements

Intel uses the following hardware and software to test the design example in a Linux system:

Intel^® Quartus^® Prime software
ModelSim^® -AE, ModelSim^® -SE, NCSim (Verilog only), VCS, and Xcelium™ simulators
Intel^® Arria^® 10 GX Transceiver Signal Integrity Development Kit for hardware testing

Functional Description

The design example consists of various components. The following block diagrams show the design components and the top-level signals of the design example.

Figure 17. Block Diagram—1G/10G Ethernet Design Example with IEEE 1588v2 Feature

Figure 18. Block Diagram—1G/10G Ethernet Design Example without IEEE 1588v2 Feature

Design Components

Table 10. Design Components of the 1G/10G Ethernet Design Example
Component	Description
LL 10GbE MAC	The Low Latency Ethernet 10G MAC Intel^® FPGA IP core with the following configuration: Speed: 1G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the design example with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY	The 1G/10G and 10GBASE-KR PHY Intel^® Arria^® 10 FPGA IP. The design example uses the 1G/10G IP variant.
Address Decoder	Decodes the addresses of the components in each Ethernet channel.
Reset Controller	Synchronizes the reset of all design components.
Transceiver Reset Controller	The Transceiver PHY Reset Controller Intel^® FPGA IP core. Resets the transceiver.
PLL	Generates clocks for all design components.
ATX PLL	Generates a TX serial clock for the Intel^® Arria^® 10 10G transceiver.
FIFO	The Avalon^® Streaming ( Avalon^® -ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH & SC_FIFO_DEPTH parameter values from 512 to 2048, under `altera_eth_fifo` instance in <Example Design>/rtl/altera_eth_channel.sv.

Clocking Scheme

The following diagrams show the clocking scheme for the design example.

Figure 19. Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature

Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.

Figure 20. Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature

Reset Scheme

The reset signals of the design example—master_reset_n and channel_reset_n[n:0]—are asynchronous and active-low signals. Asserting the master_reset_n signal resets all channels and their components; asserting the channel_reset_n[n] signal resets only the n channel and its components.

Upon power-up, reset the example design by asserting the master_reset_n signal. The following diagram shows the master reset scheme for the design example.

Figure 21. Master Reset

The following diagram shows the channel reset scheme for the design example. The mm_reset signal is used to reset the registers of the design components, whereas the datapath_reset is used to reset all digital blocks including the transceiver reset controller. The mm_reset and datapath_reset are triggered at the same time because they are tied together.

The reset csr block triggers the MAC reset only when the PHY's speed changes, which is indicated by the pcs_mode_rc signal. To always reset the MAC when the PHY link is lost, you can set the parameter PHY2MAC_RESET_EN to 1 in altera_eth_channel_1588.v/altera_eth_channel.sv

Figure 22. Channel Reset

Simulation

Table 11. Ethernet Operations
Operation	Description
Configuring the PHY speed.	Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), or 1G1000Base-X.
Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X.	Write one of the following values to the PHY's register at address offset 0x12C0. 0x01: Turn on the auto-detection mode. In this mode, the PHY automatically detects the speed. 0x11: Turn off the auto-detection mode and set the speed to 1 Gbps. 0x41: Turn off the auto-detection mode and set the speed to 10 Gbps. Example To set port 0 to 1000BASE-X: `write_32 0x02_52C0 0x11` To set port 0 to auto-detection mode: `write_32 0x02_52C0 0x01`

Test Case—Design Example with the IEEE 1588v2 Feature

The simulation test case performs the following steps:

Starts up the design example with an operating speed of 10G.
Configures the MAC, PHY, and FIFO buffer for all channels.
Waits until the design example asserts the channel_ready signal for each channel.
Sends the following packets:
- Non-PTP
- No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Sync Message,1-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
- No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
Repeats steps 2 to 4 for other operating speeds.

When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.

Figure 23. Sample Simulation Output

Test Case—Design Example without the IEEE 1588v2 Feature

The simulation test case performs the following steps:

Starts up the example design with an operating speed of 10G.
Configures the MAC, PHY, and FIFO buffer for all channels.
Waits until the example design asserts the channel_ready signal for each channel.
Sends the following packets:
- Normal data frame, 64Bytes
- SVLAN data frame, broadcast, 64Bytes
- VLAN data frame, unicast, 500Bytes
Repeats steps 2 to 4 for other operating speeds.

Figure 24. Sample Simulation Output

Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

In the Clock Control application, which is part of the development kit, set the following frequencies:

Y5—644.53125 MHz
Y6—125 MHz

Test Cases

You can run any of the following tests from the System Console.

Table 12. Hardware Test Cases
Test Case	Command	Example
PHY internal serial loopback	`TEST_PHYSERIAL_LOOPBACK` <channel> <speed_test> <burst_size>	`TEST_PHYSERIAL_LOOPBACK 0 10G 1000`
SMA loopback	For the design with the IEEE 1588v2 feature: `TEST_SMA_LB` <channel> <speed_test> <burst_size>	`TEST_SMA_LB 0 10G 1000`
SMA loopback	For the design without the IEEE 1588v2 feature: `TEST_SMA_LOOPBACK` <channel> <speed_test> <burst_size>	`TEST_SMA_LB 0 10G 1000`

Table 13. Command Parameters
Parameter	Valid Values	Description
`channel`	0 to the number of channel specified for the design	The number of channels for the test.
`speed_test`	10G, 1G	The PHY speed.
`burst_size`	—	The number of packets to generate for the test.

When the test is completed, observe the output displayed in the System Console. The following diagrams show samples of the output.

Figure 25. Sample Test Output—Packet Monitor

Figure 26. Sample Test Output—Statistics Counters

Signal Tap Debug Signals

The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below:

set_global_assignment -name ENABLE_SIGNALTAP ON

Table 14. Signal Tap Debug Signals
Component	Module Name	Signal
Top-level design example	`altera_eth_top`	`mm_clk` `ref_clk_1g` `ref_clk_10g` `channel_ready_n` `channel_reset_n` `master_reset_n`
Multi-channel wrapper	Design example without the IEEE 1588v2 feature: `altera_eth_top.altera_eth_multi_channel` Design example with the IEEE 1588v2 feature: `altera_eth_top.altera_eth_multi_channel_1588`	`pll_locked` `pll_1_locked` `pll_2_locked` (only for the design example with the IEEE 1588v2 feature) `pll_locked_10g` `pll_locked_1g`
MAC IP core	<n>`.altera_eth_10g_mac` ²	`avalon_st_tx_startofpacket` `avalon_st_tx_endofpacket` `avalon_st_tx_data` `avalon_st_tx_ready` `avalon_st_tx_valid` `avalon_st_tx_error` `avalon_st_tx_empty` `avalon_st_rx_startofpacket` `avalon_st_rx_endofpacket` `avalon_st_rx_data` `avalon_st_rx_ready` `avalon_st_rx_valid` `avalon_st_rx_error` `avalon_st_rx_empty`
PHY	<n>`.altera_eth_10gkr_phy` ²	`led_an` `led_char_err` `led_disp_err` `led_link` `mii_speed_sel` `rx_analogreset` `rx_block_lock` `rx_cal_busy` `rx_is_lockedtodata` `rx_digitalreset` `rx_data_ready` `tx_analogreset` `tx_digitalreset`
XGMII	<n>`.altera_eth_10g_mac.alt_em10g32.alt_em10g32unit` ²	`xgmii_tx_control` `xgmii_tx_data` `xgmii_rx_control` `xgmii_rx_data` `link_fault_status_xgmii_rx_data`
GMII	<n>`.altera_eth_10g_mac` ²	`gmii_tx_d` `gmii_tx_en` `gmii_tx_err` `gmii_rx_d` `gmii_rx_dv` `gmii_rx_err`

² Replace n with:

altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design example without the IEEE 1588v2 feature.
altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588 for the design example with the IEEE 1588v2 feature.

Interface Signals

Figure 27. Interface Signals of the 1G/10G Ethernet Design Example

Table 15. Clock Domains
Clock	Frequency (MHz)	Interface Signals
`xgmii_clk`	156.25	Avalon-ST interfaces Packet Classifier interface IEEE 1588v2 time-stamp interface `channel_ready[n]` (PHY interface)
`mm_clk`	125	Avalon-MM interface
`pll_ref_clk_1g`	125	`master_pulse_per_second` (ToD interface)

Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon-MM interface.

Table 16. Register Map
Byte Offset	Block
0x00_0000	Client logic
0x00_F000	Reserved
0x01_0000	Master TOD
Channel 0
0x02_0000	Reserved
0x02_4000	PHY
0x02_7800	10G TOD
0x02_7900	1G TOD
0x02_8000	LL 10GbE MAC
Channel 1
0x03_0000	Reserved
0x03_4000	PHY
0x03_7800	10G TOD
0x03_7900	1G TOD
0x03_8000	LL 10GbE MAC
.. and so forth up to Channel 11.
0x0E_0000 onwards	Client Logic

10GBASE-R Ethernet Design Example for Intel Arria 10 Devices

The 10GBASE-R Ethernet design example demonstrates an Ethernet solution for Intel^® Arria^® 10 devices using the LL 10GbE MAC Intel^® FPGA IP core, the native PHY IP core, and a small form factor pluggable plus (SFP +) module.

Generate the design example from the Example Design tab of the LL 10GbE Intel^® FPGA IP parameter editor.

Features

Supports single Ethernet channels operating at 10G using Intel^® Arria^® 10 Native PHY.
Option to generate the design example with the 10GBASE-R register mode enabled.
140 ns round-trip latency in simulation when the register mode is enabled.
Packet monitoring on the TX and RX datapaths.
Tested with the Spirent TestCenter.

Hardware and Software Requirements

Intel^® uses the following hardware and software to test the design example in a Linux system:

Intel^® Quartus^® Prime software
ModelSim^® -AE, ModelSim^® -SE, NCSim (Verilog only), VCS, and Xcelium™ simulators
For hardware testing:
- Intel^® Arria^® 10 GX Transceiver Signal Integrity Development Kit for hardware testing
- Cables—SFP+ and fiber optic cable

Functional Description

Figure 28. Block Diagram—10GBASE-R Ethernet Design Example

Design Components

Table 17. Design Components
Component	Description
LL 10GbE MAC	The Low Latency Ethernet 10G MAC Intel^® FPGA IP core with the following configuration: Speed: 10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable 10GBASE-R register mode: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based TX and RX datapath Reset/Default To Enable: Selected Use legacy XGMII Interface: Selected. Use legacy Avalon Memory-Mapped Interface: Not Selected Use legacy Avalon Streaming Interface: Not selected The settings when the 10GBASE-R Register mode is enabled: Enable 10GBASE-R register mode: Selected Use legacy XGMII Interface: Not selected Use legacy Avalon Memory-Mapped Interface: Selected
PHY	The Transceiver Native PHY Intel^® Arria^® 10/ Intel^® Cyclone^® 10 FPGA IP configured for the 10GBASE-R protocol. The register mode preset sets the PHY's TX FIFO MODE to Fast Register. The non-register mode preset sets the PHY's TX FIFO MODE to Phase Compensation and RX FIFO MODE to 10GBASE-R.
Transceiver Reset Controller	The Transceiver PHY Reset Controller Intel^® FPGA IP core. Resets the transceiver.
Address decoder	Decodes the addresses of the components.
Reset synchronizer	Synchronizes the reset of all design components.
ATX PLL	Generates a TX serial clock for the Intel^® Arria^® 10 10G transceiver.
FIFO	Avalon^® Streaming ( Avalon^® -ST) single-clock FIFO. Buffers the RX and TX data between the MAC IP core and the client.

Clocking and Reset Scheme

Figure 29. Clocking and Reset Scheme for 10GBASE-R Design Example

Figure 30. Clocking and Reset Scheme for 10GBASE-R Design Example with the Register Mode Enabled

Simulation

The simulation test case demonstrates how the MAC and PHY configuration is changed at 10-Gbps throughput. The test case is for a single Ethernet channel.

At the end of the simulation, the simulator generates the statistics of TX and RX packets in the Transcript window.

In the Wave window, the roundtrip latency for the serial loopback is indicated by the measurement cursors that show the time taken to transmit the first data from the Avalon^® -ST TX interface to be available at the Avalon^® -ST RX interface.

Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

In the Clock Control application, which is part of the development kit, set the following frequencies:

Y5—322.265625 MHz
Y6—125 MHz

Test Cases

You can run any of the following tests from the System Console.

Table 18. Hardware Test Cases
Test Case	Command	Description
SFP+ loopback	`source gen_conf.tcl`	The generator generates and sends about 4 billion packets. Wait 6 minutes for it to complete its tasks.
	`source monitor_conf.tcl`	The monitor checks the number of good and bad packets received.
	`source show_stats.tcl`	This script displays the values of the statistics counters.
Avalon-ST loopback	`source loopback_conf.tcl`	This command enables the Avalon-ST loopback. This test is used with an external tester such as Spirent tester.

After the test is completed, observe the output displayed in the System Console.

Figure 31. Sample Test Output—Ethernet Packet Monitor

Figure 32. Sample Test Output—Statistics Counters

Signal Tap Debug Signals

The Signal Tap file is included for debugging.

This feature is disabled by default. To enable it, set the following assignment:

set_global_assignment -name ENABLE_SIGNALTAP ON

Table 19. Signal Tap Debug Signals
Component	Module Name	Signal
Top-level design example	`altera_eth_top`	`csr_clk` `ref_clk_clk` `master_reset_n` `block_lock_n` `tx_ready_export_n` `rx_ready_export_n`
Design Example	`altera_eth_top.altera_eth_10g_mac_base_r_low_latency`	`atx_pll_locked` `iopll_locked`
MAC IP core	`altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac`	`avalon_st_tx_startofpacket` `avalon_st_tx_endofpacket` `avalon_st_tx_data` `avalon_st_tx_ready` `avalon_st_tx_valid` `avalon_st_tx_error` `avalon_st_tx_empty` `avalon_st_rx_startofpacket` `avalon_st_rx_endofpacket` `avalon_st_rx_data` `avalon_st_rx_ready` `avalon_st_rx_valid` `avalon_st_rx_error` `avalon_st_rx_empty`
MAC TX	`altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_tx_top.alt_em10g32_tx_rs_layer.alt_em10g32_tx_rs_xgmii_layer_ultra`	`xgmii_tx_valid` `xgmii_tx_data` `xgmii_tx_control`
MAC RX	`altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_rx_top.alt_em10g32_rx_rs_layer.alt_em10g32_rx_rs_xgmii_ultra`	`xgmii rx valid` `xgmii rx data` `xgmii rx control` `xgmii rx link fault status`
PHY	`altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_baser`	`tx_analogreset` `tx_digitalreset` `rx_analogreset` `rx_digitalreset` `tx_cal_busy` `rx_cal_busy` `rx_is_lockedtodata` `tx_clkout`

Interface Signals

Figure 33. Interface Signals of the 10GBASE-R Ethernet Design Example

Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon-MM interface.

Table 20. Register Map
Byte Offset	Block
0x0000_0000	LL 10GbE MAC
0x0000_8000	Native PHY
0x0000_D400	RX SC FIFO
0x0000_D600	TX SC FIFO
0x0000_C000	Packet Generator and Checker
0x0000_D000 – 0xFFFF_FFFF	Client Logic

1G/2.5G Ethernet Design Example for Intel Arria 10 Devices

The 1G/2.5G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel^® FPGA IP core operating at 1G and 2.5G.

Generate the design example from the Example Design tab of the LL 10GbE Intel^® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature.

Features

Dual-speed Ethernet operation—1G and 2.5G.
Support for two channels.
Option to generate the design example with the IEEE 1588v2 feature.
Testbench and simulation script.
Tested with the Spirent TestCenter.
Option to generate design example with Partial Reconfiguration Ready.

Hardware and Software Requirements

Intel uses the following hardware and software to test the design example in a Linux system:

Intel^® Quartus^® Prime Pro Edition software (Partial Reconfiguration Ready)
ModelSim^® -AE, ModelSim^® -SE, NCSim (Verilog only), VCS, and Xcelium™ simulators
For hardware testing:
- Intel^® Arria^® 10 GX Signal Integrity Development Board (10AX115S3F45E2SGE3)—for the design example with the IEEE 1588v2 feature
- Intel^® Arria^® 10 GX Signal Integrity Development Board (10AX115S4F45E3SGE3)—for the design example without the IEEE 1588v2 feature

Note: Partial Reconfiguration Ready feature is supported from Intel^® Quartus^® Prime Pro Edition software version 17.0 onwards.

Functional Description

The design example consists of various components. The following block diagrams shows the design components and the top-level signals of the design example.

Figure 34. Block Diagram—1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

Figure 35. Block Diagram—1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature

Design Components

Table 21. Design Components
Component	Description
LL 10GbE MAC	The Low Latency Ethernet 10G MAC Intel^® FPGA IP with the following configuration: Speed: 1G/2.5G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected For the design example with the IEEE 1588v2 feature, the following additional parameters are configured: Enable time stamping: Selected Enable PTP one-step clock support: Selected Timestamp fingerprint width: 4 Time Of Day format: Enable both 96b and 64b Time of Day Format
PHY	The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP.
Transceiver Reset Controller	The Transceiver PHY Reset Controller Intel^® FPGA IP core. Resets the transceiver.
Avalon^® -MM Mux Transceiver Reconfig	Provides the transceiver reconfig block and system console access to the PHY's Avalon^® -MM interface.
Transceiver Reconfig	Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa.
ATX PLL	Generates a TX serial clock for the Intel^® Arria^® 10 2.5G transceiver.
fPLL	Generates a TX serial clock for the Intel^® Arria^® 10 1G transceiver.
Design Components for the IEEE 1588v2 Feature
IO PLL	Generates the clocks for the 1588 design components.
Master TOD	The master TOD for all channels.
TOD Synch	Synchronizes the Master TOD to all Local TODs.
Local TOD	The TOD for each channel.
Master Pulse Per Second	Returns pulse per second (pps) for all channels.
Pulse Per Second	Returns pulse per second (pps) for each channel.
PTP Packet Classifier	Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel^® FPGA IP core.

Clocking Scheme

Figure 36. Clocking Scheme for the 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

Figure 37. Clocking Scheme for the 1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature

Reset Scheme

The global reset signal of the design example is asynchronous and active-low. Asserting this signal resets all channels and their components. Upon power-up, reset the design example.

Figure 38. Reset Scheme for the 1G/2.5G Ethernet Design Example without IEEE 1588v2 Feature

Figure 39. Reset Scheme for the 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

Partial Reconfiguration Ready

When the Partial Reconfiguration Ready option is turned on, the generated hierarchy of the design example is in compliance with the partial reconfiguration flow. There is a clear separation between the hard IP and the soft IP. Hard IPs such as Native PHY, JTAG, transmitter (TX) PLL, and fPLL are instantiated at the top-level wrapper of the design example. Certain soft IPs such as transceiver reset controller and TX PLL reset controller are also instantiated at the top-level wrapper of the design example because their functions are tightly coupled to the hard IPs. A wrapper called alt_eth_pr contains the soft IP logic that you can add to the partial reconfiguration region of your design. There is no functionality change after the Partial Reconfiguration Ready option is turned on.

Figure 40. 1G/2.5G Ethernet Design Example Hierarchy Without IEEE 1588v2 Feature When the Partial Reconfiguration Ready Option is Turned Off

Figure 41. 1G/2.5G Ethernet Design Example Hierarchy Without IEEE 1588v2 Feature When the Partial Reconfiguration Ready Option is Turned On

Figure 42. Design Example Hierarchy With the IEEE 1588v2 Feature When the Partial Reconfiguration Ready Option is Turned Off

Figure 43. Design Example Hierarchy With the IEEE 1588v2 Feature When the Partial Reconfiguration Ready Option is Turned On

Simulation

Test Case—Design Example with the IEEE 1588v2 Feature

The simulation test case performs the following steps:

Starts up the design example with an operating speed of 2.5G.
Configures the MAC, PHY, and FIFO buffer for both channels.
Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for each channel.
Sends the following packets:
- Non-PTP
- No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP
- VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP
- No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP
- VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP
- Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP
Repeats steps 2 to 4 for 1G.

Figure 44. Sample Simulation Output

Test Case—Design Example without the IEEE 1588v2 Feature

The simulation test case performs the following steps:

Starts up the example design with an operating speed of 2.5G.
Configures the MAC, PHY, and FIFO buffer for both channels.
Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for both channels.
Sends the following packets:
- 64-byte packet
- 1518-byte packet
- 100-byte packet
Repeats steps 2 to 4 for 1G.

Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

In the Clock Control application, which is part of the development kit, set the following frequencies:

Y5—644.53125 MHz
Y6—125 MHz

Test Procedure

Follow these steps to test the design examples in hardware:

Run the following command in the system console to start the test.

TEST_EXT_LB <channel> <speed> <burst_size>

Example: TEST_EXT_LB 0 2.5G 1000000000

Table 22. Command Parameters
Parameter	Valid Values	Description
`channel`	0, 1	The channel number to test.
`speed`	1G, 2.5G	The PHY speed.
`burst_size`	An integer value	The number of packets to generate for the test.

When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the Ethernet packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters.
Figure 45. Sample Test Output—Ethernet Packet Monitor

Figure 46. Sample Test Output—Statistics Counters

Interface Signal

Figure 47. Interface Signals of the 1G/2.5G Ethernet Design Example

Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon-MM interface.

Table 23. Register Map
Byte Offset	Block
0x00_0000	Transceiver Reconfiguration
0x00_4000	Reserved
Channel 0
0x01_0000	MAC
0x01_8000	PHY
0x01_A000	Native PHY Reconfiguration
Channel 1
0x02_0000	MAC
0x02_8000	PHY
0x02_A000	Native PHY Reconfiguration
Traffic Controller
0x10_0000	Traffic Controller

1G/2.5G/10G Ethernet Design Example for Intel Arria 10 Devices

The 1G/2.5G/10G Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel^® FPGA IP core operating at 1G, 2.5G, and 10G.

Generate the design example from the Example Design tab of the LL 10GbE Intel^® FPGA IP parameter editor.

Features

Tri-speed Ethernet operation—1G, 2.5G, and 10G.
Support for two channels.
Testbench and simulation script.
Tested with the Spirent TestCenter.
Option to generate design example with Partial Reconfiguration Ready.

Hardware and Software Requirements

Intel uses the following hardware and software to test the design example in a Linux system:

Intel^® Quartus^® Prime Pro Edition software (Partial Reconfiguration Ready)
ModelSim^® -AE, ModelSim^® -SE, NCSim (Verilog only), VCS, and Xcelium™ simulators
For hardware testing:
- Intel^® Arria^® 10 GX Signal Integrity Development Board (10AX115S4F45E3SGE3)
- Cables—SMA cable, SFP+, and fiber optic cable

Note: Partial Reconfiguration Ready feature is supported from Intel^® Quartus^® Prime Pro Edition software version 17.0 onwards.

Functional Description

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

Figure 48. Block Diagram—1G/2.5G/10G Ethernet Design Example

Design Components

Table 24. Design Components
Component	Description
LL 10GbE MAC	The Low Latency Ethernet 10G MAC Intel^® FPGA IP core with the following configuration: Speed: 1G/2.5G/10G Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based All Legacy Ethernet 10G MAC Interfaces options: Selected
PHY	The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP.
Transceiver Reset Controller	The Transceiver PHY Reset Controller Intel^® FPGA IP core. Resets the transceiver.
Avalon^® -MM Mux Transceiver Reconfig	Provides the transceiver reconfig block and system console access to the PHY's Avalon^® -MM interface.
Transceiver Reconfig	Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.
ATX PLL	Generates a TX serial clock for the Intel^® Arria^® 10 2.5G and 10G transceiver.
fPLL	Generates a TX serial clock for the Intel^® Arria^® 10 1G transceiver.

Clocking Scheme

Figure 49. Clocking Scheme for the 1G/2.5G/10G Ethernet Design Example

Reset Scheme

The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example.

Figure 50. Reset Scheme for the 1G/2.5G/10G Ethernet Design Example

Partial Reconfiguration Ready

Figure 51. 1G/2.5G/10G Ethernet Design Example Hierarchy when the Partial Reconfiguration Ready Option is Turned Off

Figure 52. 1G/2.5G/10G Ethernet Design Example Hierarchy when the Partial Reconfiguration Ready Option is Turned On

Simulation

The simulation test case performs the following steps:

Starts up the example design with an operating speed of 10 Gbps.
Configures the MAC, PHY, and FIFO buffer for both channels.
Waits until the design example asserts the channel_tx_ready and channel_rx_readysignals for both channels.
Sends the following packets:
- 64-byte packet
- 1518-byte packet
- 100-byte packet
Repeats steps 2 to 4 for 1G and 2.5G.

Figure 53. Sample Simulation Output

Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

In the Clock Control application, which is part of the development kit, set the following frequencies:

Y5—644.53125 MHz
Y6—125 MHz

Test Procedure

Follow these steps to test the design examples in hardware:

Run the following command in the system console to start the test.

TEST_EXT_LB <channel> <speed> <burst_size>

Example: TEST_EXT_LB 0 10G 80000000

Table 25. Command Parameters
Parameter	Valid Values	Description
`channel`	0, 1	The channel number to test.
`speed`	1G, 2.5G, 10G	The PHY speed.
`burst_size`	An integer value	The number of packets to generate for the test.

When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters.
Figure 54. Sample Test Output—Packet Monitor

Figure 55. Sample Test Output—Statistics Counters

Interface Signals

Figure 56. Interface Signals of the 1G/2.5G/10G Ethernet Design Example

Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon-MM interface.

Table 26. Register Map
Byte Offset	Block
0x00_0000	Transceiver Reconfiguration
0x00_4000	Reserved
Channel 0
0x01_0000	MAC
0x01_8000	PHY
0x01_A000	Native PHY Reconfiguration
Channel 1
0x02_0000	MAC
0x02_8000	PHY
0x02_A000	Native PHY Reconfiguration
Traffic Controller
0x10_0000	Traffic Controller

10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel Arria 10 Devices

The 10G USXGMII Ethernet design example demonstrates the functionalities of the LL 10GbE MAC Intel^® FPGA IP core operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.

Generate the design example from the Example Design tab of the LL 10GbE Intel^® FPGA IP parameter editor.

Features

Supports dual Ethernet channel operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.
On the transmit and receive paths:
- Provides packet monitoring system.
- Reports Ethernet MAC statistics counter.
Supports testing using different types of Ethernet packet transfer protocol.

Hardware and Software Requirements

Intel uses the following hardware and software to test the design example in a Linux system:

Intel^® Quartus^® Prime software
ModelSim^® -AE, ModelSim^® -SE, NCSim (Verilog only), VCS, and Xcelium™ simulators
For hardware testing:
- Intel^® Arria^® 10 GX Signal Integrity Development Board (10AX115S4F45E3SGE3)
- Cables—SFP+ and fiber optic cable

Functional Description

The design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.

Figure 57. Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example

Design Components

Table 27. Design Components
Component	Description
LL 10GbE MAC	The Low Latency Ethernet 10G MAC Intel^® FPGA IP core with the following configuration: Speed: 10M/100M/1G/2.5G/5G/10G (USXGMII) Datapath options: TX & RX Enable ECC on memory blocks: Not selected Enable supplementary address: Selected Enable statistics collection: Selected Statistics counters: Memory-based TX and RX datapath Reset/Default To Enable: Selected Use legacy XGMII Interface: Not selected Use legacy Avalon Memory-Mapped Interface: Not selected Use legacy Avalon Streaming Interface: Selected
PHY	The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP with the following configuration: Speed: 10M/100M/1G/2.5G/5G/10G Connect to MGBASE-T PHY: Not selected Connect to NBASE-T PHY: Selected Reference clock frequency for 10GbE (MHz): 644.53125 Enable Altera Debug Master Endpoint: Not selected Enable capability registers: Not selected Enable control and status registers: Not selected Enable PRBS soft accumulators: Not selected
Channel address decoder	Decodes the addresses of the components in each Ethernet channel.
Multi-channel address decoder	Decodes the addresses of the components used by all channels, such as the Master ToD module.
Top address decoder	Decodes the addresses of the top-level components, such as the Traffic Controller.
Transceiver Reset Controller	The Transceiver PHY Reset Controller Intel^® FPGA IP core. Resets the transceiver.
ATX PLL	Generates a TX serial clock for the Intel^® Arria^® 10 10G transceiver.
Core fPLL	Generates clocks for all design components.

Clocking Scheme

Figure 58. Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example

Reset Scheme

The global reset signal of the design example is asynchronous and active-high. Asserting this signal resets all channels and their components. Upon power-up, reset the design example.

Figure 59. Reset Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example

Simulation

Test Case

The simulation test case performs the following steps:

Starts up the example design with an operating speed of 10G.
Configures the MAC, PHY, and FIFO buffer for both channels.
Waits until the design example asserts the channel_tx_ready and channel_rx_readysignals for both channels.
Sends the following packets:
- 64-byte packet
- 1518-byte packet
- 100-byte packet
Repeats steps 2 to 4 for 10M, 100M, 1G, 2.5G, and 5G.

Figure 60. Sample Simulation Output

Hardware Testing

Follow the procedure at the provided link to test the design example in the selected hardware.

In the Clock Control application, which is part of the development kit, set the following frequencies:

Y5—644.53125 MHz
Y6—125 MHz

Test Procedure

Follow these steps to test the design examples in hardware:

Run the following command in the system console to enable PHY serial loopback on Channel 0:
SET_CHANNEL_BASE_ADDR 0

SETPHY_SERIAL_LLPBK

Note: This step is only required if you are using Intel^® Arria^® 10 GX SI Development Board rev E and above, and on Channel 0 only.

Run the following command in the system console to start the test.

TEST_EXT_LB <channel> <speed> <burst_size>

Example: TEST_EXT_LB 0 10G 80000000

Table 28. Command Parameters
Parameter	Valid Values	Description
`channel`	0, 1	The channel number to test.
`speed`	10M, 100M, 1G, 2P5G, 5G, 10G	The PHY speed.
`burst_size`	An integer value	The number of packets to generate for the test.

When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the Ethernet packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters.

Figure 61. Sample Test Output—Ethernet Packet Monitor

Figure 62. Sample Test Output—Statistics Counters

Interface Signals

Figure 63. Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example

Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon^® -MM interface.

Table 29. Register Map
Byte Offset	Block
0x00_0000	Reserved
Channel 0
0x02_0000	Reserved
0x02_4000	PHY
0x02_6000	Native PHY Reconfiguration
0x02_8000	MAC
Channel 1
0x03_0000	Reserved
0x03_4000	PHY
0x03_6000	Native PHY Reconfiguration
0x03_8000	MAC
Traffic Controller
0x10_0000	Traffic Controller

Interface Signals Description

Use the following tables to find the description of the signals in the design example. The pinout diagram for each design example specifies the width of the signals.

Clock and Reset Interface Signals

Table 30. Clock and Reset Interface Signals
Signal	Direction	Width	Description
`mm_clk` `csr_clk`	In	1	125 MHz configuration clock for the Avalon^® -MM interface.
`mac_clk`	In	1	156.25 MHz configuration clock for the Avalon^® -ST interface.
`refclk`	In	1	125 MHz reference clock for the TX PLLs.
`pll_ref_clk_1g[]`	In	`[NUM_UNSHARED_CHANNELS]`	Reference clock for the TX PLL in 1G mode. Frequency is 125 MHz.
`pll_ref_clk_10g[]`	In	`[NUM_UNSHARED_CHANNELS]`	Reference clock for the TX PLL in 10G mode. Frequency is 644.53125 MHz.
`cdr_ref_clk_1g[]`	In	`[NUM_UNSHARED_CHANNELS]`	Reference clock for the RX PLL in 1G mode. Frequency is 125 MHz.
`cdr_ref_clk_10g[]`	In	`[NUM_UNSHARED_CHANNELS]`	Reference clock for the RX PLL in 10G mode. Frequency is 644.53125 MHz.
`xgmii_clk`	Out	`[NUM_UNSHARED_CHANNELS]`	Clock used for single data rate (SDR) XGMII TX and RX interface in between MAC and PHY. Whenever present, this clock is also used for Avalon-ST interface. Frequency is 156.25 MHz.
`rx_pma_clkout`	Out	1	CDR recovered clock.
`rx_recovered_clk`	Out	`[NUM_CHANNELS]`	RX clock, recovered from the RX data.
`tx_xcvr_clk`	Out	1	322.265625 MHz clock for the TX datapath.
`rx_xcvr_clk`	Out	1	322.265625 MHz clock for the RX datapath.
`rx_xcvr_half_clk`	Out	1	161.133 MHz synchronous clock derived from `rx_xcvr_clk`
`tx_xcvr_half_clk`	Out	1	161.133 MHz synchronous clock derived from `tx_xcvr_clk`
`ref_clk_clk`	In	1	322.265625 MHz clock for the TX PLL.
`core_clk_312`	Out	1	312.5 MHz clock for the fast domain.
`core_clk_156`	Out	1	156.25-MHz clock for the slow domain.
`channel_reset_n`	In	`[NUM_CHANNELS]`	Assert this asynchronous and active-low signal to reset individual Ethernet channel. This does not impact the components running at multi_channel level, for example, master TOD, master PPS and fPLLs.
`master_reset_n`	In	1	Assert this asynchronous and active-low signal to reset the whole design example.
`reset`	In	1	Assert this asynchronous and active-high signal to reset the whole design example.
`csr_rst_n`	In	1	Active-low reset signal for the Avalon^® -MM interface.
`tx_rst_n`	In	1	Active-low reset signal for the TX datapath.
`rx_rst_n`	In	1	Active-low reset signal for the RX datapath.
`tx_digitalreset`	In	`[NUM_CHANNELS]`	Asynchronous and active-high signal to reset PCS TX portion of the transceiver PHY.
`rx_digitalreset`	In	`[NUM_CHANNELS]`	Asynchronous and active-high signal to reset PCS RX portion of the transceiver PHY.
`tx_analogreset`	In	`[NUM_CHANNELS]`	Asynchronous and active-high signal to reset PMA TX portion of the transceiver PHY.
`rx_analogreset`	In	`[NUM_CHANNELS]`	Asynchronous and active-high signal to reset PMA RX portion of the transceiver PHY.

Avalon -MM Interface Signals

Table 31. Avalon^® -MM Interface Signals
Signal	Direction	Description
`write` `csr_write` `csr_mac_write` `csr_phy_write` `csr_rcfg_write` `csr_native_phy_rcfg_write` `csr_master_tod_write`	In	Assert this signal to request a write.
`read` `csr_read` `csr_mac_read` `csr_phy_read` `csr_rcfg_read` `csr_native_phy_rcfg_read` `csr_master_tod_read`	In	Assert this signal to request a read.
`address` `csr_address` `csr_mac_address` `csr_phy_address` `csr_rcfg_address` `csr_native_phy_rcfg_address` `csr_master_tod_address`	In	Use this bus to specify the register address you want to read from or write to.
`writedata` `csr_writedata` `csr_mac_writedata` `csr_phy_writedata` `csr_rcfg_writedata` `csr_native_phy_rcfg_writedata` `csr_master_tod_writedata`	In	Carries the data to be written to the specified register.
`readdata` `csr_readdata` `csr_mac_readdata` `csr_phy_readdata` `csr_rcfg_readdata` `csr_native_phy_rcfg_readdata` `csr_master_tod_readdata`	Out	Carries the data read from the specified register.
`waitrequest` `csr_waitrequest` `csr_mac_waitrequest` `csr_phy_waitrequest` `csr_native_phy_rcfg_waitrequest` `csr_master_tod_waitrequest`	Out	When asserted, this signal indicates that the IP core is busy and not ready to accept any read or write requests.

Avalon -ST Interface Signals

Table 32. Avalon^® -ST Interface Signals
Signal	Direction	Width	Description
`avalon_st_tx_startofpacket[]`	In	`[NUM_CHANNELS]`	Assert this signal to indicate the beginning of the TX data.
`avalon_st_tx_endofpacket[]`	In	`[NUM_CHANNELS]`	Assert this signal to indicate the end of the TX data.
`avalon_st_tx_valid[]`	In	`[NUM_CHANNELS]`	Assert this signal to indicate that `avalon_st_tx_data[]` and other signals on this interface are valid.
`avalon_st_tx_ready[]`	Out	`[NUM_CHANNELS]`	When asserted, indicates that the MAC IP core is ready to accept data. The reset value of this signal is non-deterministic.
`avalon_st_tx_error[]`	In	`[NUM_CHANNELS]`	Assert this signal to indicate that the current TX packet contains errors.
`avalon_st_tx_data[][]`	In	`[NUM_CHANNELS][m]`	TX data from the client. m is 64 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 32.
`avalon_st_tx_empty[][]`	In	`[NUM_CHANNELS][m]`	Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data. m is 3 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 2. 0x0—All bytes are valid. 0x1—The last byte is invalid. 0x2—The last two bytes are invalid. 0x3—The last three bytes are invalid.
`avalon_st_rx_startofpacket[]`	Out	`[NUM_CHANNELS]`	When asserted, indicates the beginning of the RX data.
`avalon_st_rx_endofpacket[]`	Out	`[NUM_CHANNELS]`	When asserted, indicates the end of the RX data.
`avalon_st_rx_valid[]`	Out	`[NUM_CHANNELS]`	When asserted, indicates that the avalon_st_rx_ data[] signal and other signals on this interface are valid.
`avalon_st_rx_ready[]`	In	`[NUM_CHANNELS]`	Assert this signal when the client is ready to accept data.
`avalon_st_rx_error[][]`	Out	`[NUM_CHANNELS][6]`	When set to 1, the respective bits indicate an error type: Bit 0—PHY error. For 10 Gbps, the data on `xgmii_rx_data` contains a control error character (FE). For 10 Mbps,100 Mbps,1 Gbps, `gmii_rx_err` or `mii_rx_err` is asserted. Bit 1—CRC error. The computed CRC value differs from the received CRC. Bit 2—Undersized frame. The receive frame length is less than 64 bytes. Bit 3—Oversized frame. The receive frame length is more than `MAX_FRAME_SIZE`. Bit 4—Payload length error. The actual frame payload length is different from the value in the length/type field. Bit 5—Overflow error. The receive FIFO buffer is full while it is still receiving data from the MAC IP core.
`avalon_st_rx_data[][]`	Out	`[NUM_CHANNELS][m]`	RX data to the client. m is 64 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 32.
`avalon_st_rx_empty[][]`	Out	`[NUM_CHANNELS][m]`	Contains the number of empty bytes during the cycle that contain the end of the RX data. m is 3 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 2.
`avalon_st_tx_status_valid[]`	Out	`[NUM_CHANNELS]`	When asserted, this signal qualifies the `avalon_st_txstatus_data[]` and `avalon_st_txstatus_error[]` signals.
`avalon_st_tx_status_data[][]`	Out	`[NUM_CHANNELS][40]`	Contains information about the TX frame. Bits 0 to 15—Payload length. Bits 16 to 31—Packet length. Bit 32—When set to 1, indicates a stacked VLAN frame. Bit 33—When set to 1, indicates a VLAN frame. Bit 34—When set to 1, indicates a control frame. Bit 35—When set to 1, indicates a pause frame. Bit 36—When set to 1, indicates a broadcast frame. Bit 37—When set to 1, indicates a multicast frame. Bit 38—When set to 1, indicates a unicast frame. Bit 39—When set to 1, indicates a PFC frame.
`avalon_st_tx_status_error[][]`	Out	`[NUM_CHANNELS][7]`	When set to 1, the respective bit indicates the following error type in the RX frame. Bit 0—Undersized frame. Bit 1—Oversized frame. Bit 2—Payload length error. Bit 3—Unused. Bit 4—Underflow. Bit 5—Client error. Bit 6—Unused. The error status is invalid when an overflow occurs.
`avalon_st_rxstatus_valid[]`	Out	`[NUM_CHANNELS]`	When asserted, this signal qualifies the `avalon_st_rxstatus_data[]` and `avalon_st_rxstatus_error[]` signals. The MAC IP core asserts this signal in the same clock cycle the `avalon_st_rx_endofpacket` signal is asserted.
`avalon_st_rxstatus_data[][]`	Out	`[NUM_CHANNELS][40]`	Contains information about the RX frame. Bits 0 to 15—Payload length. Bits 16 to 31—Packet length. Bit 32—When set to 1, indicates a stacked VLAN frame. Bit 33—When set to 1, indicates a VLAN frame. Bit 34—When set to 1, indicates a control frame. Bit 35—When set to 1, indicates a pause frame. Bit 36—When set to 1, indicates a broadcast frame. Bit 37—When set to 1, indicates a multicast frame. Bit 38—When set to 1, indicates a unicast frame. Bit 39—When set to 1, indicates a PFC frame.
`avalon_st_rxstatus_error[][]`	Out	`[NUM_CHANNELS][7]`	When set to 1, the respective bit indicates the following error type in the RX frame. Bit 0—Undersized frame. Bit 1—Oversized frame. Bit 2—Payload length error. Bit 3—Unused. Bit 4—Underflow. Bit 5—Client error. Bit 6—Unused. The error status is invalid when an overflow occurs.
`avalon_st_pause_data[][]`	In	`[NUM_CHANNELS][2]`	This signal takes effect when the register bits, `tx_pauseframe_enable[2:1]`, are both set to the default value 0. Set this signal to the following values to trigger the corresponding actions. 0x0—Stops pause frame generation. 0x1—Generates an XON pause frame. 0x2—Generates an XOFF pause frame. The MAC IP core sets the pause quanta field in the pause frame to the value in the `tx_pauseframe_quanta` register. 0x3—Reserved.

PHY Interface Signals

Table 33. PHY Interface Signals
Signal	Direction	Description
`rx_serial_data`	In	RX serial input data
`tx_serial_data`	Out	TX serial output data

Status Interface

Table 34. Status Interface Signals
Signal	Direction	Description
`block_lock`	Out	Asserted when the link synchronization is successful.
`led_an` `ethernet_1g_an`	Out	Asserted when auto-negotiation is completed.
`led_char_err` `ethernet_1g_char_err`	Out	Asserted when a 10-bit character error is detected in the RX data.
`led_disp_err` `ethernet_1g_disp_err`	Out	Asserted when a 10-bit running disparity error is detected in the RX data.
`channel_ready` `channel_tx_ready` `channel_rx_ready` `tx_ready_export` `rx_ready_export`	Out	Asserted when the channel is ready for data transmission.
`atx_pll_locked`	Out	Asserted when the TX PLL is locked.

IEEE 1588v2 Timestamp Interface Signals

Table 35. IEEE 1588v2 Timestamp Interface Signals
Signal	Direction	Width	Description
`tx_egress_timestamp_96b_valid[]`	Out	`[NUM_CHANNELS]`	When asserted, this signal qualifies the timestamp, `tx_egress_timestamp_96b_data[]`, and the fingerprint, `tx_egress_timestamp_96b_fingerprint[]`, of the TX frame.
`tx_egress_timestamp_96b_data[][]`	Out	`[NUM_CHANNELS][96]`	Carries the 96-bit egress timestamp in the following format: Bits 48 to 95: 48-bit seconds field Bits 16 to 47: 32-bit nanoseconds field Bits 0 to 15: 16-bit fractional nanoseconds field
`tx_egress_timestamp_96b_fingerprint[][]`	Out	`[NUM_CHANNELS][TSTAMP_FP_WIDTH]`	Specifies the fingerprint of the TX frame that the 96-bit timestamp is for.
`tx_egress_timestamp_64b_valid[]`	Out	`[NUM_CHANNELS]`	When asserted, this signal qualifies the timestamp, `tx_egress_timestamp_64b_data[]`, and the fingerprint, `tx_egress_timestamp_64b_fingerprint[]`, of the TX frame.
`tx_egress_timestamp_64b_data[][]`	Out	`[NUM_CHANNELS][64]`	Carries the 64-bit egress timestamp in the following format: Bits 16 to 63: 48-bit nanoseconds field Bits 0 to 15: 16-bit fractional nanoseconds field
`tx_egress_timestamp_64b_fingerprint[][]`	Out	`[NUM_CHANNELS][TSTAMP_FP_WIDTH]`	Specifies the fingerprint of the TX frame that the 64-bit timestamp is for.
`rx_ingress_timestamp_96b_valid[]`	Out	`[NUM_CHANNELS]`	When asserted, this signal qualifies the timestamp, `rx_ingress_timestamp_96b_data[]`. The MAC IP core asserts this signal in the same clock cycle it asserts `avalon_st_rx_startofpacket`.
`rx_ingress_timestamp_96b_data[][]`	Out	`[NUM_CHANNELS][96]`	Carries the 96-bit ingress timestamp in the following format: Bits 48 to 95: 48-bit seconds field Bits 16 to 47: 32-bit nanoseconds field Bits 0 to 15: 16-bit fractional nanoseconds field
`rx_ingress_timestamp_64b_valid[]`	Out	`[NUM_CHANNELS]`	When asserted, this signal qualifies the timestamp, `rx_ingress_timestamp_64b_data[]`. The MAC IP core asserts this signal in the same clock cycle it asserts `avalon_st_rx_startofpacket`.
`rx_ingress_timestamp_64b_data[][]`	Out	`[NUM_CHANNELS][64]`	Carries the 64-bit ingress timestamp in the following format: Bits 16 to 63: 48-bit nanoseconds field Bits 0 to 15: 16-bit fractional nanoseconds field

Packet Classifier Interface Signals

Table 36. Packet Classifier Interface Signals
Signal	Direction	Width	Description
`tx_egress_timestamp_request_in_valid[]`	In	`[NUM_CHANNELS]`	Assert this signal to request timestamping for the TX frame. This signal must be asserted in the same clock cycle `avalon_st_tx_startofpacket` is asserted.
`tx_egress_timestamp_request_in_fingerprint[][]`	In	`[NUM_CHANNELS][TSTAMP_FP_WIDTH]`	Use this bus to specify the fingerprint that validates the timestamp for the incoming packet.
`clock_operation_mode_mode[][]`	In	`[NUM_CHANNELS][2]`	Use this signal to specify the clock mode. 00: Ordinary clock 01: Boundary clock 10: End to end transparent clock 11: Peer to peer transparent clock
`pkt_with_crc_mode[]`	In	`[NUM_CHANNELS]`	Use this signal to specify whether or not a packet contains CRC. 0: Packet contains CRC 1: Packet does not contain CRC
`tx_ingress_timestamp_valid[]`	In	`[NUM_CHANNELS]`	Indicates whether or not the residence time can be updated. 0: Prevents update for residence time 1: Allows update for residence time based on decoded results When this signal is deasserted, the `tx_etstamp_ins_ctrl_out_residence_ti me_update` signal also gets deasserted.
`tx_ingress_timestamp_96b_data[][]`	In	`[NUM_CHANNELS][96]`	96-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet.
`tx_ingress_timestamp_64b_data[][]`	In	`[NUM_CHANNELS][64]`	64-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet.
`tx_ingress_timestamp_format[]`	In	`[NUM_CHANNELS]`	The format of the timestamp for calculating the residence time. 0: 96 bits 1: 64 bits This signal must be aligned to the start of an incoming packet.

ToD Interface Signals

Table 37. ToD Interface Signals
Signal	Direction	Width	Description
`master_pulse_per_second`	Out	1	Pulse per second (PPS) from the master PPS module. The signal stay asserted for 10 ms.
`start_tod_sync[]`	In	`[NUM_CHANNELS]`	Use this signal to trigger the TOD synchronization process. The time of day of the local TOD is synchronized to the time of day of the master TOD. The synchronization process continues as long as this signal remains asserted.
`pulse_per_second_10g[]`	Out	`[NUM_CHANNELS]`	PPS from the 10G PPS module of channel n. The signal stay asserted for 10 ms.
`pulse_per_second_1g[]`	Out	`[NUM_CHANNELS]`	PPS from the 1G PPS module of channel n. The signal stay asserted for 10 ms.

Configuration Registers Description

Low Latency Ethernet 10G MAC

This topic lists the byte offsets the MAC registers.

Table 38. Primary MAC Address
Byte Offset	R/W	Name	HW Reset
0x2008	RW	`primary_mac_addr0`	0x0
0x200C	RW	`primary_mac_addr1`	0x0

Table 39. TX Configuration and Status Registers
Byte Offset	R/W	Name	HW Reset
0x4000	RW	`tx_packet_control`	0x0
0x4004	RO	`tx_packet_status`	0x0
0x4100	RW	`tx_pad_control`	0x1
0x4200	RW	`tx_crc_control`	0x3
0x4400	RW	`tx_preamble_control`	0x0
0x6004	RW	`tx_frame_maxlength`	0x5EE(1518)
0x4300	RO	`tx_underflow_counter0`	0x0
0x4304	RO	`tx_underflow_counter1`	0x0

Table 40. Flow Control Registers
Byte Offset	R/W	Name	HW Reset
0x4500	RW	`tx_pauseframe_control`	0x0
0x4504	RW	`tx_pauseframe_quanta`	0x0
0x4508	RW	`tx_pauseframe_enable`	0x1
0x4680	RW	`tx_pfc_priority_enable`	0x0
0x4600	RW	`pfc_pause_quanta_0`	0x0
0x4604	RW	`pfc_pause_quanta_1`	0x0
0x4608	RW	`pfc_pause_quanta_2`	0x0
0x460C	RW	`pfc_pause_quanta_3`	0x0
0x4610	RW	`pfc_pause_quanta_4`	0x0
0x4614	RW	`pfc_pause_quanta_5`	0x0
0x4618	RW	`pfc_pause_quanta_6`	0x0
0x461C	RW	`pfc_pause_quanta_7`	0x0
0x4640	RW	`pfc_holdoff_quanta_0`	0x1
0x4644	RW	`pfc_holdoff_quanta_1`	0x1
0x4648	RW	`pfc_holdoff_quanta_2`	0x1
0x464C	RW	`pfc_holdoff_quanta_3`	0x1
0x4650	RW	`pfc_holdoff_quanta_4`	0x1
0x4654	RW	`pfc_holdoff_quanta_5`	0x1
0x4658	RW	`pfc_holdoff_quanta_6`	0x1
0x465C	RW	`pfc_holdoff_quanta_7`	0x1

Table 41. RX Configuration and Status Registers
Byte Offset	R/W	Name	HW Reset
0x0000	RW	`rx_transfer_control`	0x0
0x0004	RO	`rx_transfer_status`	0x0
0x0100	RW	`rx_padcrc_control`	0x1
0x0200	RW	`rx_crccheck_control`	0x2
0x0400	RW	`rx_custom_preamble_forward`	0x0
0x0500	RW	`rx_preamble_control`	0x0
0x2000	RW	`rx_frame_control`	0x3
0x2004	RW	`rx_frame_maxlength`	1518
0x2010	RW	`rx_frame_spaddr0_0`	0x0
0x2014	RW	`rx_frame_spaddr0_1`	0x0
0x2018	RW	`rx_frame_spaddr1_0`	0x0
0x201C	RW	`rx_frame_spaddr1_1`	0x0
0x2020	RW	`rx_frame_spaddr2_0`	0x0
0x2024	RW	`rx_frame_spaddr2_1`	0x0
0x2028	RW	`rx_frame_spaddr3_0`	0x0
0x202C	RW	`rx_frame_spaddr3_1`	0x0
0x2060	RW	`rx_pfc_control`	0x1
0x0300	RO	`rx_pktovrflow_error`	0x0

Table 42. TX Timestamp Registers
Byte Offset	R/W	Name	HW Reset
0x4440	RW	`tx_period_10G`	0x33333
0x4448	RW	`tx_fns_adjustment_10G`	0x0
0x444C	RW	`tx_ns_adjustment_10G`	0x0
0x4460	RW	`tx_period_mult_speed`	0x80000
0x4468	RW	`tx_fns_adjustment_mult_speed`	0x0
0x446C	RW	`tx_ns_adjustment_mult_speed`	0x0

Table 43. RX Timestamp Registers
Byte Offset	R/W	Name	HW Reset
0x0440	RW	`rx_period_10G`	0x33333
0x0448	RW	`rx_fns_adjustment_10G`	0x0
0x044C	RW	`rx_ns_adjustment_10G`	0x0
0x0460	RW	`rx_period_mult_speed`	0x80000
0x0468	RW	`rx_fns_adjustment_mult_speed`	0x0
0x046C	RW	`rx_ns_adjustment_mult_speed`	0x0

Table 44. TX and RX Statistics Registers
Byte Offset	R/W	Name	HW Reset
0x7000	RO	`tx_stats_clr`	0x0
0x3000	RO	`rx_stats_clr`	0x0
0x7008:0x700C	RO	`tx_stats_framesOK`	0x0
0x3008:0x300C	RO	`rx_stats_framesOK`	0x0
0x7010:0x7014	RO	`tx_stats_framesErr`	0x0
0x3010:0x3014	RO	`rx_stats_framesErr`	0x0
0x7018:0x701C	RO	`tx_stats_framesCRCErr`	0x0
0x3018:0x301C	RO	`rx_stats_framesCRCErr`	0x0
0x7020:0x7024	RO	`tx_stats_octetsOK`	0x0
0x3020:0x3024	RO	`rx_stats_octetsOK`	0x0
0x7028:0x702C	RO	`tx_stats_pauseMACCtrl_Frames`	0x0
0x3028:0x302C	RO	`rx_stats_pauseMACCtrl_Frames`	0x0
0x7030:0x7034	RO	`tx_stats_ifErrors`	0x0
0x3030:0x3034	RO	`rx_stats_ifErrors`	0x0
0x7038:0x703C	RO	`tx_stats_unicast_FramesOK`	0x0
0x3038:0x303C	RO	`rx_stats_unicast_FramesOK`	0x0
0x7040:0x7044	RO	`tx_stats_unicast_FramesErr`	0x0
0x3040:0x3044	RO	`rx_stats_unicast_FramesErr`	0x0
0x7048:0x704C	RO	`tx_stats_multicast_FramesOK`	0x0
0x3048:0x304C	RO	`rx_stats_multicast_FramesOK`	0x0
0x7050:0x7054	RO	`tx_stats_multicast_FramesErr`	0x0
0x3050:0x3054	RO	`rx_stats_multicast_FramesErr`	0x0
0x7058:0x705C	RO	`tx_stats_broadcast_FramesOK`	0x0
0x3058:0x305C	RO	`rx_stats_broadcast_FramesOK`	0x0
0x7060:0x7064	RO	`tx_stats_broadcast_FramesErr`	0x0
0x3060:0x3064	RO	`rx_stats_broadcast_FramesErr`	0x0
0x7068:0x706C	RO	`tx_stats_etherStatsOctets`	0x0
0x3068:0x306C	RO	`rx_stats_etherStatsOctets`	0x0
0x7070:0x7074	RO	`tx_stats_etherStatsPkts`	0x0
0x3070:0x3074	RO	`rx_stats_etherStatsPkts`	0x0
0x7078:0x707C	RO	`tx_stats_etherStatsUndersizePkts`	0x0
0x3078:0x307C	RO	`rx_stats_etherStatsUndersizePkts`	0x0
0x7080:0x7084	RO	`tx_stats_etherStatsOversizePkts`	0x0
0x3080:0x3084	RO	`rx_stats_etherStatsOversizePkts`	0x0
0x7088:0x708C	RO	`tx_stats_etherStatsPkts64Octets`	0x0
0x3088:0x308C	RO	`rx_stats_etherStatsPkts64Octets`	0x0
0x7090:0x7094	RO	`tx_stats_etherStatsPkts65to127Octets`	0x0
0x3090:0x3094	RO	`rx_stats_etherStatsPkts65to127Octets`	0x0
0x7098:0x709C	RO	`tx_stats_etherStatsPkts128to255Octets`	0x0
0x3098:0x309C	RO	`rx_stats_etherStatsPkts128to255Octets`	0x0
0x70A0:0x70A4	RO	`tx_stats_etherStatsPkts256to511Octets`	0x0
0x30A0:0x30A4	RO	`rx_stats_etherStatsPkts256to511Octets`	0x0
0x70A8:0x70AC	RO	`tx_stats_etherStatsPkts512to1023Octets`	0x0
0x30A8:0x30AC	RO	`rx_stats_etherStatsPkts512to1023Octets`	0x0
0x70B0:0x70B4	RO	`tx_stats_etherStatPkts1024to1518Octets`	0x0
0x30B0:0x30B4	RO	`rx_stats_etherStatPkts1024to1518Octets`	0x0
0x70B8:0x70BC	RO	`tx_stats_etherStatsPkts1519toXOctets`	0x0
0x30B8:0x30BC	RO	`rx_stats_etherStatsPkts1519toXOctets`	0x0
0x70C0:0x70C4	RO	`tx_stats_etherStatsFragments`	0x0
0x30C0:0x30C4	RO	`rx_stats_etherStatsFragments`	0x0
0x70C8:0x70CC	RO	`tx_stats_etherStatsJabbers`	0x0
0x30C8:0x30CC	RO	`rx_stats_etherStatsJabbers`	0x0
0x70D0:0x70D4	RO	`tx_stats_etherStatsCRCErr`	0x0
0x30D0:0x30D4	RO	`rx_stats_etherStatsCRCErr`	0x0
0x70D8:0x70DC	RO	`tx_stats_unicastMACCtrlFrames`	0x0
0x30D8:0x30DC	RO	`rx_stats_unicastMACCtrlFrames`	0x0
0x70E0:0x70E4	RO	`tx_stats_multicastMACCtrlFrames`	0x0
0x30E0:0x30E4	RO	`rx_stats_multicastMACCtrlFrames`	0x0
0x70E8:0x70EC	RO	`tx_stats_broadcastMACCtrlFrames`	0x0
0x30E8:0x30EC	RO	`rx_stats_broadcastMACCtrlFrames`	0x0
0x70F0:0x70F4	RO	`tx_stats_PFCMACCtrlFrames`	0x0
0x30F0:0x30F4	RO	`rx_stats_PFCMACCtrlFrames`	0x0

PHY

This topic lists the byte offsets of the Intel^® Arria^® 10 1G/10G registers.

Table 45. PMA Registers
Byte Offset	Bit	R/W	Name
0x1110	1	RW	`reset_tx_digital`
	2	RW	`reset_rx_analog`
	3	RW	`reset_rx_dgital`
0x1184	0	RW	`phy_serial_loopback`
0x1190	0	RW	`pma_rx_set_locktodata`
0x1194	0	RW	`pma_rx_set_locktoref`
0x1198	0	RO	`pma_rx_is_lockedtodata`
0x119C	0	RO	`pma_rx_is_lockedtoref`
0x12A0	0	RW	`tx_invpolarity`
	1	RW	`rx_invpolarity`
	2	RW	`rx_bitreversal_enable`
	3	RW	`rx_bytereversal_enable`
	4	RW	`force_electrical_idle`
0x12A4	0	R	`rx_syncstatus`
	1	R	`rx_patterndetect`
	2	R	`rx_rlv`
	3	R	`rx_rmfifodatainserted`
	4	R	`rx_rmfifodatadeleted`
	5	R	`rx_disperr`
	6	R	`rx_errdetect`

Table 46. PCS Registers
Byte Offset	Bit	R/W	Name
0x1200		RW	`Indirect_addr`
0x1204	2	RW	`RCLR_ERRBLK_CNT`
0x1204	3	RW	`RCLR_BER_COUNT`
0x1208	1	RO	`HI_BER`
	2	RO	`BLOCK_LOCK`
	3	RO	`TX_FULL`
	4	RO	`RX_FULL`
	7	RO	`Rx_DATA_READY`

Table 47. Intel^® Arria^® 10 GMII PCS Registers
Byte Offset	Bit	R/W	Name
0x1240	9	RW	`RESTART_AUTO_NEGOTIATION`
	12	RW	`AUTO_NEGOTIATION_ENABLE`
	15	RW	`RESET`
0x1244	2	R	`LINK_STATUS`
	3	R	`AUTO_NEGOTIATION_ ABILITY`
	5	R	`AUTO_NEGOTIATION_ COMPLETE`
0x1250	5	RW	`FD`
	6	RW	`HD`
	8:7	RW	`PS2,PS1`
	13:12	RW	`RF2,RF1`
	14	R0	`ACK`
	15	RW	`NP`
0x1254	5	R	`FD`
	6	R	`HD`
	8:7	R	`PS2,PS1`
	13:12	R	`RF2,RF1`
	14	R	`ACK`
	15	R	`NP`
0x1258	0	R	`LINK_PARTNER_AUTO_NEGOTIATION_ABLE`
0x1258	1	R	`PAGE_RECEIVE`
0x1288	15:0	RW	`AN link timer[15:0]`
0x128C	4:0	RW	`AN link timer[4:0]`
0x1290	0	RW	`SGMII_ENA`
	1	RW	`USE_SGMII_AN`
	3:2	RW	`SGMII_SPEED`

Transceiver Reconfiguration

Table 49. Transceiver Reconfiguration Register Map
Word Offset	Name	Bits	Description	Access	HW Reset
0x00	`logical_channel_number`	[9:0]	The logical number of the reconfiguration block.	RW	0x000
0x00	`logical_channel_number`	[31:10]	Reserved	—	—
0x01	`control`	[1:0]	Specify the new operating speed: 00: 1 Gbps 01: 2.5 Gbps 10: Reserved 11: 10 Gbps	RW	0x00
		[15:2]	Reserved	—	0x000
		[16]	Writing 1 to this bit when it is 0 starts the reconfiguration process. The bit clears when the process is completed.	RWC	0x0
		[31:17]	Reserved	—	0x000000
0x02	`status`	[0]	When set to 1, indicates the reconfiguration process is in progress.	RO	0x0
0x02	`status`	[31:1]	Reserved	—	—

TOD

Table 50. **TOD Register Map**
Byte Offset	Name	Bits	Description	Access	HW Reset
0x0000	`SecondsH`	[15:0]	The upper 16 bits of the second field.	RW	0x0
0x0000	`SecondsH`	[31:16]	Reserved.	—	—
0x0004	`SecondsL`	32	The lower 32 bits of the second field.	RW	0x0
0x0008	`NanoSec`	30	The nanosecond field.	RW	0x0
0x0010	`Period`	[15:0]	The time of day. The period in fractional nanosecond.	RW	n ³
		[19:16]	The time of day. The period in nanosecond.	RW	n ³
		[31:20]	Reserved.	—	—
0x0014	`AdjustPeriod`	[15:0]	The offset adjustment period. The period in fractional nanosecond.	RW	0x0
		[19:16]	The offset adjustment period. The period in nanosecond.	RW	0x0
		[31:20]	Reserved.	—	—
0x0018	`AdjustCount`	[19:0]	The number of adjusted period in clock cycles.	RW	0x0
0x0018	`AdjustCount`	[31:20]	Not used.	—	—

³ The default value for the period depends on the frequency of the PHY speed. For example, if frequency is 125 MHz, the period is 8 ns (PERIOD_NS = 0x0008 and PERIOD_FNS = 0x0000).

Document Revision History for Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide

Document Version	Intel^® Quartus^® Prime Version	Changes
2018.05.16	18.0	Renamed the document as Low Latency Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide. Updated the 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices chapter: Added 10M/100M speed support for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example. Updated all references to 10G USXGMII references to 10M/100M/1G/2.5G/5G/10G (USXGMII). Updated Table: Command Parameters. Updated Table: Register Map to include byte offset for Native PHY Reconfiguration block. Added support for Xcelium simulator. Updated the procedure steps of the Compiling and Testing the Design in Hardware topic. Restructured description for Hardware Testing topics for all design example chapters. Updated Table: Clock and Reset Interface Signals. Updated the following Figures: Directory Structure for the Design Example Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature Master Reset Interface Signals of the 10GBASE-R Ethernet Design Example Master Reset for 10M/100M/1G/10G and 1G/10G Ethernet design examples. Updated for latest branding standards. Made editorial updates throughout the document.
2018.03.28	17.1	Updated 10G USXGMII Ethernet Design Example section: Corrected Y5 value from 322.265625 MHz to 644.53125 Mhz in the Hardware Testing topic. Updated Figure: Clocking Scheme for 10G USXGMII Ethernet Design Example. Added a step on Test Procedure topic to enable PHY serial loopback on Channel 0.

Date	Version	Changes
November 2017	2017.11.13	Updated Figure: Example Design Tab. Updated the Clocking and Reset scheme for 10GBASE-R Design example: Added `tx_coreclkin` and `rx_coreclkin` clock ports to the PHY block.
November 2017	2017.11.06	Renamed the document as Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Arria 10 Devices. Updated the descriptions for FIFO component in the "Design Components" table for the 10M/100M/1G/ 10G, 1G/10G, 10BASE-R, 1G/2.5G, 1G/2.5G/10G, and 10G USXGMII ethernet design examples. Added notes to clarify that the IOPLL input reference clock is sourcing from input clock through global clock network in the Clocking Schemes topics for the 10M/100M/1G/ 10G, 1G/10G, and 10GBASE-R ethernet design examples. Updated the Quick Start Guide section: Updated Figures: Example Design Tab and Block Diagram of the Hardware Setup Updated the "Directory and File Description" table. Removed rtl directory from the "Directory and File Description" table. Changed heading title of the Design Parameters Description topic to Design Example Parameters. Changed heading title of the Design Parameters Description topic to Design Example Parameters. Updated the "Parameters in the Example Design Tab" table: Added Enable ADME support parameter and description. Updated the descriptions for Generate File Format and Select Board parameters. Updated the Procedure subtopic under Compiling and Simulating the Design topic. Updated the 10M/100M/1G/10G Ethernet Design Example chapter: Renamed the topic Multi-speed 10M – 10G Ethernet Design Examples to 10M/100M/1G/10G Ethernet Design Example. Updated the 10BASE-R Ethernet Design Example chapter: Renamed the topic 10BASE-R Design Examples to 10BASE-R Ethernet Design Examples. Updated Figure: Block Diagram—10GBASE-R Design Example Updated `csr_clk` value from 100 MHz to 125 MHz in the "Clocking and Reset Scheme for 10GBASE-R Design Example" figure. Updated "Register Map" table: Updated the byte offset values for RX SC FIFO and TX SC FIFO. Updated the description in the Hardware Description topic. Updated 1G/2.5G Ethernet Design Example chapter: Updated the 1G/2.5G Ethernet Design Example topic. Added Topic—Partial Reconfiguration Ready. Updated the 1G/2.5G/10G Ethernet Design Example chapter: Updated the 1G/2.5G/10G Ethernet Design Example topic. Added Topic—Partial Reconfiguration Ready. Added Figure—Sample Simulation Output Updated 10G USXGMII Ethernet Design Examples chapter: Updated the 10G USXGMII Ethernet Design Example topic. Updated "Design Components" table: Added channel address decoder, multi-channel address decoder, and top address decoder components. Updated the description in the Hardware Description topic. Added Figure—Sample Simulation Output Updated "Clocking Scheme for 10G USXGMII Ethernet Design Example" and "Reset Scheme for 10G USXGMII Ethernet Design Example" figures: Updated the reference clock value from 644.53125 MHz to 322.265625 MHz. Updated "Clock and Reset Interface Signals table: Updated the description for the `mm_clk` and `csr_clk` signals. Updated PHY topic: Updated "PMA Registers" table: Updated bit values of five registers. Updated "Intel Arria 10 GMII PCS Registers" table: Updated bit names for 0x1240. Merged the 10G TOD, and 1G TOD topics with the Master TOD and changed heading title to ToD. Updated "ToD Register Map" table: Added bits information. Updated for latest branding standards. Made editorial updates throughout the document.
June 2017	2017.06.20	Corrected typographical errors in the Design Components topic for 1G/2.5G Ethernet design example.
June 2017	2017.06.19	Rebranded as Intel. Updated the "Transceiver Reconfiguration Register Map" table to include operation speed support of 10 Gbps for `control` register. Added Partial Reconfiguration Ready feature for the 1G/2.5G and 1G/2.5G/10G Ethernet design examples. Renamed the document as Intel Arria 10 Low Latency Ethernet 10G MAC Design Example User Guide.
October 2016	2016.10.31	Changed the title of the document to be consistent with other design example user guides. Adjusted the rows in the table that describes the design parameters description to match the parameter editor user interface. Updated the steps to run the simulation scripts to clarify that the commands are to be run at the system's command prompt. Updated the simulation script command for VCS and NCSim from "`source tb_run.sh`" to "`sh tb_run.sh`". Updated the features of the 10BASE-R design example from supporting single channel to now support dual channels. Added related information links that provide more information about the Avalon-ST and IEEE 1588v2 interface clocks.
May 2016	2016.05.20	Updated the Quick Start Guide to include the latest GUI and procedure steps. Updated the Channel Reset diagrams and description for the Multi-speed 10M - 10G and 1G/10G Ethernet design examples. Updated the Clocking diagram the Multi-speed 10M - 10G Ethernet design example with the IEEE 1588v2 feature. Updated the SignalTap Signals topic for the Multi-speed 10M - 10G, 1G/10G, and 10GBASE-R Ethernet design examples. Updated Chapter 4 to include a 10GBASE-R design example with the Register Mode disabled. Added Chapters 5, 6, and 7, which document 4 new design examples. Updated Interface Signals appendix.
December 2015	2015.12.14	Initial release.