Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.3.1. Agent Interface

The Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP provides an Avalon® memory-mapped agent interface to read and write to PR configuration registers.

Table 18.  Data/CSR Memory Map Format
Name Address Offset Access Description
PR_DATA 0x00 Write

Every data write to this address indicates this bitstream is sent to the IP core.

Performing a read on this address returns all 0's.

PR_CSR 0x01 Read or Write Control and status registers.
Version Register 0x02 Read-Only

Read-only SW version register. Register is currently 0xAA500003

PR Bitstream ID 0x03 Read-Only Read-only PR POF ID register
Table 19.  PR_CSR Control and Status Bits
Bit Offset Description
0

Read and write control register for pr_start signal. Refer to Ports for details on the pr_start signal.

pr_start = PR_CSR[0]

The IP core deasserts PR_CSR[0] to value 0 automatically, one clock cycle after the PR_CSR[0] asserts. This streamlines the flow to avoid manual assertion and de-assertion of this register to control pr_start signal.

1 Reserved.
2-4

Read-only status register for status[2:0] signal.

PR_CSR[4:2] = status[2:0]

Refer to Ports for details on the status signals.

5

Read and clear bit for interrupt.

If you enable the interrupt interface, reading this bit returns the value of the irq signal. Writing a 1 clears the interrupt.

If you disable the interrupt interface, reading this bit always returns a value of 0.

6-31 Reserved bits. Depends on the Avalon® memory-mapped data bus width.

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