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1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
1. Introduction to the Avalon® Interface Specifications
|Intel® Quartus® Prime Design Suite 20.1|
Avalon® interfaces simplify system design by allowing you to easily connect components in Intel® FPGA. The Avalon® interface family defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices. Components available in Platform Designer incorporate these standard interfaces. Additionally, you can incorporate Avalon® interfaces in custom components, enhancing the interoperability of designs.
This specification defines all the Avalon® interfaces. After reading this specification, you should understand which interfaces are appropriate for your components and which signal roles to use for particular behaviors. This specification defines the following seven interfaces:
- Avalon® Streaming Interface ( Avalon® -ST)—an interface that supports the unidirectional flow of data, including multiplexed streams, packets, and DSP data.
- Avalon® Memory Mapped Interface ( Avalon® -MM)—an address-based read/write interface typical of Host-Agent connections.
- Avalon® Conduit Interface— an interface type that accommodates individual signals or groups of signals that do not fit into any of the other Avalon® types. You can connect conduit interfaces inside a Platform Designer system. Alternatively, you can export them to connect to other modules in the design or to FPGA pins.
- Avalon® Tri-State Conduit Interface ( Avalon® -TC) —an interface to support connections to off-chip peripherals. Multiple peripherals can share pins through signal multiplexing, reducing the pin count of the FPGA and the number of traces on the PCB.
- Avalon® Interrupt Interface—an interface that allows components to signal events to other components.
- Avalon® Clock Interface—an interface that drives or receives clocks.
- Avalon® Reset Interface—an interface that provides reset connectivity.
A single component can include any number of these interfaces and can also include multiple instances of the same interface type.
Note: Avalon® interfaces are an open standard. No license or royalty is required to develop and sell products that use or are based on Avalon® interfaces.
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