Avalon® Interface Specifications

ID 683091
Date 1/24/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1. Interrupt Sender

An interrupt sender drives a single interrupt signal to an interrupt receiver. The timing of the irq signal must be synchronous to the rising edge of its associated clock. irq has no relationship to any transfer on any other interface. irq must be asserted until acknowledged on the associated Avalon® -MM agent interface.

Interrupts are component specific. The receiver typically determines the appropriate response by reading an interrupt status register from an Avalon® -MM agent interface.