Avalon® Interface Specifications

ID 683091
Date 1/24/2022

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3.5.4. Pipelined Transfers

Avalon® -MM pipelined read transfers increase the throughput for synchronous agent devices that require several cycles to return data for the first access. Such devices can typically return one data value per cycle for some time thereafter. New pipelined read transfers can start before readdata for the previous transfers is returned.

A pipelined read transfer has an address phase and a data phase. A host initiates a transfer by presenting the address during the address phase. A agent fulfills the transfer by delivering the data during the data phase. The address phase for a new transfer (or multiple transfers) can begin before the data phase of a previous transfer completes. The delay is called pipeline latency. The pipeline latency is the duration from the end of the address phase to the beginning of the data phase.

Transfer timing for wait-states and pipeline latency have the following key differences:

  • Wait-states—Wait-states determine the length of the address phase. Wait-states limit the maximum throughput of a port. If a agent requires one wait-state to respond to a transfer request, the port requires two clock cycles per transfer.
  • Pipeline Latency—Pipeline latency determines the time until data is returned independently of the address phase. A pipelined agent with no wait-states can sustain one transfer per cycle. However, the agent may require several cycles of latency to return the first unit of data.

Wait-states and pipelined reads can be supported concurrently. Pipeline latency can be either fixed or variable.