Avalon® Interface Specifications

ID 683091
Date 1/24/2022

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5.12. Protocol Details

Packet data transfer follows the same protocol as the typical data transfer with the addition of the startofpacket, endofpacket, and empty.
Figure 32. Packet TransferThe following figure illustrates the transfer of a 17-byte packet from a source interface to a sink interface, where readyLatency=0. This timing diagram illustrates the following events:
  1. Data transfer occurs on cycles 1, 2, 4, 5, and 6, when both ready and valid are asserted.
  2. During cycle 1, startofpacket is asserted. The first 4 bytes of packet are transferred.
  3. During cycle 6, endofpacket is asserted. empty has a value of 3. This value indicates that this is the end of the packet and that 3 of the 4 symbols are empty. In cycle 6, the high-order byte, data[31:24] drives valid data.