Avalon® Interface Specifications

ID 683091
Date 1/24/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.9. Reset Source

Table 7.  Reset Output Signal RolesThe reset_req signal is an optional signal that you can use to prevent memory content corruption by performing reset handshake prior to an asynchronous reset assertion.
Signal Role Width Direction Required Description
reset_n 1 Output Yes Resets the internal logic of an interface or component to a user-defined state.
reset_req 1 Output Optional Enables reset request generation, which is an early signal that is asserted before reset assertion. Once asserted, this cannot be deasserted until the reset is completed.