Avalon® Interface Specifications

ID 683091
Date 1/24/2022

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3.5.1. Typical Read and Write Transfers

This section describes a typical Avalon® -MM interface that supports read and write transfers with agent-controlled waitrequest. The agent can stall the interconnect for as many cycles as required by asserting the waitrequest signal. If a agent uses waitrequest for either read or write transfers, the agent must use waitrequest for both.

A agent typically receives address, byteenable, read or write, and writedata after the rising edge of the clock. A agent asserts waitrequest before the rising clock edge to hold off transfers. When the agent asserts waitrequest, the transfer is delayed. While waitrequest is asserted, the address and other control signals are held constant. Transfers complete on the rising edge of the first clk after the agent interface deasserts waitrequest.

There is no limit on how long a agent interface can stall. Therefore, you must ensure that a agent interface does not assert waitrequest indefinitely. The following figure shows read and write transfers using waitrequest.


waitrequest can be decoupled from the read and write request signals. waitrequest may be asserted during idle cycles. An Avalon® -MM host may initiate a transaction when waitrequest is asserted and wait for that signal to be deasserted. Decoupling waitrequest from read and write requests may improve system timing. Decoupling eliminates a combinational loop including the read, write, and waitrequest signals. If even more decoupling is required, use the waitrequestAllowance property. waitrequestAllowance is available starting with the Quartus® Prime Pro v17.1 Stratix® 10 ES Editions release.

Figure 7. Read and Write Transfers with Waitrequest

The numbers in this timing diagram, mark the following transitions:

  1. address, byteenable, and read are asserted after the rising edge of clk. The agent asserts waitrequest, stalling the transfer.
  2. waitrequest is sampled. Because waitrequest is asserted, the cycle becomes a wait-state. address, read, write, and byteenable remain constant.
  3. The agent deasserts waitrequest after the rising edge of clk. The agent asserts readdata and response.
  4. The host samples readdata, response and deasserted waitrequest completing the transfer.
  5. address, writedata, byteenable, and write signals are asserted after the rising edge of clk. The agent asserts waitrequest stalling the transfer.
  6. The agent deasserts waitrequest after the rising edge of clk.
  7. The agent captures write data ending the transfer.