Avalon® Interface Specifications

ID 683091
Date 1/24/2022

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3.5.5. Burst Transfers

A burst executes multiple transfers as a unit, rather than treating every word independently. Bursts may increase throughput for agent ports that achieve greater efficiency when handling multiple words at a time, such as SDRAM. The net effect of bursting is to lock the arbitration for the duration of the burst. A bursting Avalon® -MM interface that supports both reads and writes must support both read and write bursts.

Bursting Avalon® -MM interfaces include a burstcount output signal. If a agent has a burstcount input, the agent is burst capable.

The burstcount signal behaves as follows:

  • At the start of a burst, burstcount presents the number of sequential transfers in the burst.
  • For width <n> of burstcount, the maximum burst length is 2(<n>-1).The minimum legal burst length is one.

To support agent read bursts, a agent must also support:

  • Wait states with the waitrequest signal.
  • Pipelined transfers with variable latency with the readdatavalid signal.

At the start of a burst, the agent sees the address and a burst length value on burstcount. For a burst with an address of <a> and a burstcount value of <b>, the agent must perform <b> consecutive transfers starting at address <a>. The burst completes after the agent receives (write) or returns (read) the <b th > word of data. The bursting agent must capture address and burstcount only once for each burst. The agent logic must infer the address for all but the first transfers in the burst. A agent can also use the input signal beginbursttransfer, which the interconnect asserts on the first cycle of each burst.