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1. Introduction to the Avalon® Interface Specifications 2. Avalon® Clock and Reset Interfaces 3. Avalon® Memory-Mapped Interfaces 4. Avalon® Interrupt Interfaces 5. Avalon® Streaming Interfaces 6. Avalon® Streaming Credit Interfaces 7. Avalon® Conduit Interfaces 8. Avalon® Tristate Conduit Interface A. Deprecated Signals B. Document Revision History for the Avalon® Interface Specifications
2.1. Avalon® Clock Sink Signal Roles 2.2. Clock Sink Properties 2.3. Associated Clock Interfaces 2.4. Avalon® Clock Source Signal Roles 2.5. Clock Source Properties 2.6. Reset Sink 2.7. Reset Sink Interface Properties 2.8. Associated Reset Interfaces 2.9. Reset Source 2.10. Reset Source Interface Properties
5.1. Terms and Concepts 5.2. Avalon® Streaming Interface Signal Roles 5.3. Signal Sequencing and Timing 5.4. Avalon® -ST Interface Properties 5.5. Typical Data Transfers 5.6. Signal Details 5.7. Data Layout 5.8. Data Transfer without Backpressure 5.9. Data Transfer with Backpressure 5.10. Packet Data Transfers 5.11. Signal Details 5.12. Protocol Details
184.108.40.206.1. minimumResponseLatency Timing Diagram with readdatavalid or writeresponsevalid
For interfaces with readdatavalid or writeresponsevalid, the default a one-cycle minimumResponseLatency can lead to difficulty closing timing on Avalon® -MM hosts.
The following timing diagrams show the behavior for a minimumResponseLatency of 1 or 2 cycles. Note that the actual response latency can also be greater than the minimum allowed value as these timing diagrams illustrate.
Figure 17. minimumResponseLatency Equals One Cycle
Figure 18. minimumResponseLatency Equals Two Cycles
Interfaces with the same minimumResponseLatency are interoperable without any adaptation. If the host has a higher minimumResponseLatency than the agent, use pipeline registers to compensate for the differences. The pipeline registers should delay readdata from the agent. If the agent has a higher minimumResponseLatency than the host, the interfaces are interoperable without adaptation.
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