Avalon® Interface Specifications

ID 683091
Date 1/24/2022

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Document Table of Contents minimumResponseLatency Timing Diagram with readdatavalid or writeresponsevalid

For interfaces with readdatavalid or writeresponsevalid, the default a one-cycle minimumResponseLatency can lead to difficulty closing timing on Avalon® -MM hosts.

The following timing diagrams show the behavior for a minimumResponseLatency of 1 or 2 cycles. Note that the actual response latency can also be greater than the minimum allowed value as these timing diagrams illustrate.
Figure 17. minimumResponseLatency Equals One Cycle
Figure 18. minimumResponseLatency Equals Two Cycles


Interfaces with the same minimumResponseLatency are interoperable without any adaptation. If the host has a higher minimumResponseLatency than the agent, use pipeline registers to compensate for the differences. The pipeline registers should delay readdata from the agent. If the agent has a higher minimumResponseLatency than the host, the interfaces are interoperable without adaptation.