Avalon® Interface Specifications

ID 683091
Date 1/24/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.5.6.2. Avalon® -MM Read and Write Responses Timing Diagram

The following diagram shows command acceptance and command issue order for Avalon® -MM read and write responses. Because the read and write interfaces share the response signal, an interface cannot issue or accept a write response and a read response in the same clock cycle.

Read responses, send one response for each readdata. A read burst length of <N> results in <N> responses.

Write responses, send one response for each write command. A write burst results in only one response. The agent interface sends the response after accepting the final write transfer in the burst. When an interface includes the writeresponsevalid signal, all write commands must complete with write responses.

Figure 16.  Avalon® -MM Read and Write Responses Timing Diagram