Introduction to Intel® FPGA IP Cores

ID 683102
Date 10/04/2021
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1.9.4.1. Generating a Combined Simulator Setup Script ( Intel® Quartus® Prime Pro Edition)

You can run the Generate Simulator Setup Script for IP command to generate a combined simulator setup script.
Note: This feature is available in the Intel® Quartus® Prime Pro Edition software for all devices. This feature is available in the Intel® Quartus® Prime Standard Edition software for only Intel® Arria® 10 devices.

Source this combined script from a top-level simulation script. Click Tools > Generate Simulator Setup Script for IP (or use of the ip-setup-simulation utility at the command-line) to generate or update the combined scripts, after any of the following occur:

  • IP core initial generation or regeneration with new parameters
  • Intel® Quartus® Prime software version upgrade
  • IP core version upgrade
To generate a combined simulator setup script for all project IP cores for each simulator:
  1. Generate, regenerate, or upgrade one or more IP core. Refer to Generating IP Cores or Upgrading IP Cores.
  2. Click Tools > Generate Simulator Setup Script for IP (or run the ip-setup-simulation utility). Specify the Output Directory and library compilation options. Click OK to generate the file. By default, the files generate into the /<project directory>/<simulator>/ directory using relative paths.
  3. To incorporate the generated simulator setup script into your top-level simulation script, refer to the template section in the generated simulator setup script as a guide to creating a top-level script:
    1. Copy the specified template sections from the simulator-specific generated scripts and paste them into a new top-level file.
    2. Remove the comments at the beginning of each line from the copied template sections.
    3. Specify the customizations you require to match your design simulation requirements, for example:
      • Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level file. The top-level entity of your simulation is often a testbench that instantiates your design. Then, your design instantiates IP cores or Platform Designer systems. Set the value of TOP_LEVEL_NAME to the top-level entity.
      • If necessary, set the QSYS_SIMDIR variable to point to the location of the generated IP simulation files.
      • Compile the top-level HDL file (for example, a test program) and all other files in the design.
      • Specify any other changes, such as using the grep command-line utility to search a transcript file for error signatures, or e-mail a report.
  4. Re-run Tools > Generate Simulator Setup Script for IP (or ip-setup-simulation) after regeneration of an IP variation.
    Table 10.  Simulation Script Utilities
    Utility Syntax
    ip-setup-simulation generates a combined, version-independent simulation script for all Intel® FPGA IP cores in your project. The command also automates regeneration of the script after upgrading software or IP versions. Use the compile-to-work option to compile all simulation files into a single work library if your simulation environment requires. Use the --use-relative-paths option to use relative paths whenever possible.
    ip-setup-simulation
     --quartus-project=<my proj>
     --output-directory=<my_dir>
     --use-relative-paths
     --compile-to-work

    --use-relative-paths and --compile-to-work are optional. For command-line help listing all options for these executables, type: <utility name> --help.

    ip-make-simscript generates a combined simulation script for all IP cores that you specify on the command line. Specify one or more .spd files and an output directory in the command. Running the script compiles IP simulation models into various simulation libraries.
    ip-make-simscript 
     --spd=<ipA.spd,ipB.spd> 
     --output-directory=<directory>
    ip-make-simscript generates a combined simulation script for all IP cores and subsystems that you specify on the command line.
    ip-make-simscript 
    --system-files=<ipA.ip, ipB.ip> 
    --output-directory=<directory>