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Visible to Intel only — GUID: mwh1409958271399
Ixiasoft
Visible to Intel only — GUID: mwh1409958271399
Ixiasoft
1.4. IP General Settings
The following settings control how the Intel® Quartus® Prime software manages IP cores in a project:
Setting | Description | Location |
---|---|---|
Maximum Platform Designer memory usage size | Increase if you experience slow processing for large systems, or for out of memory errors. | Tools > Options > IP Settings Or Tasks pane > Settings > IP Settings |
IP generation HDL preference | The parameter editor generates the HDL you specify for IP variations. | |
IP Regeneration Policy | Controls when synthesis files regenerate for each IP variation. Typically, you Always regenerate synthesis files for IP cores after making changes to an IP variation. | |
Generate IP simulation model when generating IP | Enables automatic generation of simulation models every time you generate the IP. | |
Use available processors for parallel generation of Quartus project IPs | Directs Platform Designer to generate IPs in parallel, using the number of processors that you specify in the Compilation Process Settings pane of the Intel® Quartus® Prime project settings. | |
Additional project and global IP search locations. | The Intel® Quartus® Prime software searches for IP cores in the project directory, in the Intel® Quartus® Prime installation directory, and in the IP search path. | Tools > Options > IP Catalog Search Locations Or Tasks pane > Settings > IP Catalog Search Locations |