Introduction to Intel® FPGA IP Cores

ID 683102
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.9.4.1.1. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts

Follow these steps to incorporate the generated ActiveHDL* or Riviera Pro* simulation scripts into a top-level project simulation script.
  1. The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, sim_top.do.
    # # Start of template 
    # # If the copied and modified template file is "aldec.do", run it as: 
    # # vsim -c -do aldec.do 
    # # 
    # # Source the generated sim script 
    # source rivierapro_setup.tcl 
    # # Compile eda/sim_lib contents first 
    # dev_com 
    # # Override the top-level name (so that elab is useful) 
    # set TOP_LEVEL_NAME top 
    # # Compile the standalone IP. 
    # com 
    # # Compile the top-level 
    # vlog -sv2k5 ../../top.sv 
    # # Elaborate the design. 
    # elab 
    # # Run the simulation 
    # run 
    # # Report success to the shell 
    # exit -code 0 
    # # End of template
  2. Delete the first two characters of each line (comment and space):
    # Start of template 
    # If the copied and modified template file is "aldec.do", run it as: 
    # vsim -c -do aldec.do 
    # 
    # Source the generated sim script 
    source rivierapro_setup.tcl 
    # Compile eda/sim_lib contents first 
    dev_com 
    # Override the top-level name (so that elab is useful) 
    set TOP_LEVEL_NAME top 
    # Compile the standalone IP. 
    com 
    # Compile the top-level 
    vlog -sv2k5 ../../top.sv 
    # Elaborate the design. 
    elab 
    # Run the simulation 
    run 
    # Report success to the shell 
    exit -code 0
    # End of template
  3. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example:
    set TOP_LEVEL_NAME sim_top
     vlog –sv2k5 ../../sim_top.sv
  4. If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
  5. Run the new top-level script from the generated simulation directory:
    vsim –c –do <path to sim_top>.tcl