Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
Public

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3.5.1. Registers

The Partial Reconfiguration Region Controller IP core performs the following operations in a partial reconfiguration:
Figure 66. Freeze Control Block PR Handshake Timing
Figure 67. Register States and Programming Model
Table 37.  Register Map
Name Address Offset Access Description
freeze_csr_status 0x00 Read-Only Freeze status register.
csr_ctrl 0x01 Read or Write Control register to enable and disable freeze.
freeze_illegal_req 0x02 Read or Write High on any bit indicates an illegal request during the freeze state.
freeze_reg_version 0x03 Read-Only Read-only version register. This register is currently 0xAD000003.
Table 38.  freeze_csr_status
Bit Fields Access Default Value Description
31:2 Reserved N/A 0x0 Reserved bits. Reading these bits always returns zeros.
1 unfreeze_status R 0

Hardware sets this bit to 1 after the PR region returns start_ack to indicate successful start of the persona.

Hardware clears this bit to 0 when the unfreeze_req bit is low.

This bit is 1 when bridges and other PR region outputs release from reset.

0 freeze_status R 0

Hardware sets this bit to 1 after the PR region returns the stop_ack signal to indicate that the PR region is ready to enter the frozen state

Hardware clears this bit to 0 when the freeze_req bit is low.

This bit is 0 when bridges and other PR region outputs release from reset.

Table 39.  freeze_csr_ctrl
Bit Fields Access Default Value Description
31:3 Reserved N/A 0x0 Reserved bits. Reading these bits always returns zeros.
2 unfreeze_req R/W 0

Write 1 to this bit to request unfreezing the PR region interfaces.

Hardware clears this bit after unfreeze_status is high.

Write 0 to this bit to terminate the unfreeze request.

Do not assert this bit and the freeze_req bit at the same time. If both freeze_req and unfreeze_req assert at the same time, it is an invalid operation.

1 reset_req R/W 0

Write 1 to start resetting the PR persona.

Write 0 to stop resetting the PR persona.

0 freeze_req R/W 0

Write 1 to this bit to start freezing the PR region interfaces.

Hardware clears this bit after freeze_status is high.

Write 0 to this bit to terminate the freeze request if the PR region never returns stop_ack after this bit asserts.

Do not assert this bit and the unfreeze_req bit at the same time. Asserting freeze_req and unfreeze_req simultaneously is an invalid operation.

Table 40.  freeze_illegal_request
Bit Fields Access Default Value Description
31:n Reserved N/A 0x0 Reserved bits. Reading these bits always returns zeros.
n-1:0 illegal_request R/W 0

High on any bit of this bus indicates a read or write issue by a static region master when an Avalon® memory-mapped slave freeze bridge is in the freeze state. Identify which freeze bridge has an illegal request by checking each bit on the bus.

For example, when illegal_request bit 2 is high, an illegal request occurred in the freeze bridge that connects to interface freeze_conduit_in2

This bus triggers the interrupt signal. Write 1 to clear this bit. n is the number of bridges.

Table 41.  freeze_reg_version
Bit Fields Access Default Value Description
31:0 Version Register Read-Only AD000003 This register bit indicates the CSR register version number. Currently the CSR register is version 0xAD000003.

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