Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
Public

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2.6.4.1. Adding the Partial Reconfiguration Controller Intel FPGA IP

You can customize and instantiate the Partial Reconfiguration Controller Intel FPGA IP from the IP Catalog (Tools > IP Catalog).

The Partial Reconfiguration Controller Intel FPGA IP interfaces with the Secure Device Manager (SDM) to manage the bitstream source. The SDM performs authentication and decompression on the configuration data. You can use this IP core in an Intel® Agilex™ or Intel® Stratix® 10 design when performing partial reconfiguration with an internal PR host, Nios® II processor, PCI Express* , or Ethernet interface.

Figure 9. Partial Reconfiguration Controller ( Avalon® Streaming Interface)
2

The Intel® Quartus® Prime software supports PR over the core interface using the PR Controller IP core, or PR over the JTAG device pins. PR over JTAG pins does not require instantiation of the Partial Reconfiguration Controller Intel FPGA IP.

2 Avalon memory-mapped interface variant also available.

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