3.3.9. PR Control Block Signals
Carries the configuration bitstream.
|pr_done||1||Output||Indicates that the PR process is complete.|
|pr_ready||1||Output||Indicates that the control block is ready to accept PR data from the control logic.|
|pr_error||1||Output||Indicates a partial reconfiguration error.|
|pr_request||1||Input||Indicates that the PR process is ready to begin.|
Determines whether you are performing the partial reconfiguration internally, or through pins.
- You can specify a configuration width of 8, 16, or 32 bits, but the interface always uses 32 pins.
- All the inputs and outputs are asynchronous to the PR clock (clk), except data signal. data signal is synchronous to clk signal.
- PR clock must be free-running.
- data signal must be 0 while waiting for ready signal.
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