Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

Download
ID 683834
Date 1/11/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.3. Interrupt Interface

If you enable the Avalon® Memory Mapped agent interface, you can use the optional interrupt interface of the Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP.

The IP core asserts irq during the following events:

Table 20.  Interrupt Interface Events
Status Code Event
3'b001 PR_ERROR occurred.
3'b010 CRC_ERROR occurred.
3'b011 The IP core detects an incompatible bitstream.
3'b101 The result of a successful PR operation.

After irq asserts, the host performs one or more of the following:

  • Query for the status of the PR IP core; PR_CSR[4:2].
  • Carry out some action, such as error reporting.
  • Once the interrupt is serviced, clear the interrupt by writing a "1" to PR_CSR[5].

Did you find the information on this page useful?

Characters remaining:

Feedback Message