Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2.2. Parameters

The Partial Reconfiguration Controller Intel® FPGA IP supports customization of the following parameters.

Table 13.   Partial Reconfiguration Controller Intel FPGA IP Parameter Settings




Enable Avalon-ST sink or Avalon-MM slave interface Avalon-ST/Avalon-MM

Enables the controller's Avalon streaming sink or Avalon memory-mapped agent interface.

Input data width <bits>

Specifies the size of the controller's data conduit interface in bits. The IP supports device widths of 32 and 64. The Avalon memory-mapped slave interface supports 32-bits only.

Enable interrupt interface


Enables interrupt assertion for detection of incompatible bitstream, CRC_ERROR, PR_ERROR, or successful partial reconfiguration. Upon interrupt, query PR_CSR[3:1] for status. Write a 1 to PR_CSR[4] to clear the interrupt. Use only together with the Avalon® memory-mapped agent interface.
Enable Protocol Checker Yes/No Reads out the error bit from the CSR register (PR_CSR[6]).
Enable SDM FW Error Reporting Yes/No Enables the SDM firmware error reporting ports and CSR. Enables the additional pr_fw_handshake and pr_fw_response ports in Avalon streaming mode, and can be read out from the CSR register (base address offsets 3 and 4) in Avalon memory-mapped mode.
Note: This parameter is only supported for Intel® Agilex™ devices.
Figure 39. Parameter Editor