Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.3.8.1. PR Control Block and CRC Block VHDL Component Declaration

The following example shows manual instantiation of the PR control block and the CRC block in your Intel® Arria® 10 PR design:
  1. Use the code sample below, containing the component declaration in VHDL. This code performs the PR function from within the core (code block within Core_Top).
    module Chip_Top is port (
    	--User I/O signals (excluding signals that relate to PR)
    	..
    	..
    )
    -- Following shows the connectivity within the Chip_Top module
    Core_Top : Core_Top
    port_map (
    	..
    	..
    );
    
    m_pr : twentynm_prblock
    port map(
    	clk => dclk,
    	corectl =>'1', --1 - when using PR from inside
    	--0 - for PR from pins; You must also enable
    	-- the appropriate option in Quartus Prime settings
    	prrequest => pr_request,
    	data => pr_data,
    	error => pr_error,
    	ready => pr_ready,
    	done => pr_done
    );
    
    m_crc : twentynm_crcblock
    port map(
    	shiftnld => '1', --If you want to read the EMR register when
    	clk => dummy_clk, --error occurrs, refer to AN539 for the
    	--connectivity forthis signal. If you only want
    	--to detect CRC errors, but plan to take no
    	--further action, you can tie the shiftnld
    	--signal to logical high.
    	crcerror => crc_error
    );
    Note: This VHDL example is adaptable for Verilog HDL instantiation.
  2. Add additional ports to Core_Top to connect to both components.
  3. Follow these rules when connecting the PR control block to the rest of your design:
    • Set the corectl signal to ‘1’ (when using partial reconfiguration from core) or to ‘0’ (when using partial reconfiguration from pins).
    • The corectl signal must match the Enable PR pins option setting in the Device and Pin Options dialog box (Assignments > Device > Device and Pin Options).
    • When performing partial reconfiguration from pins, the Fitter automatically assigns the PR unassigned pins. Assign all the dedicated PR pins using Pin Planner ( Assignments > Pin Planner) or Assignment Editor (Assignments > Assignment Editor).
    • When performing partial reconfiguration from the core logic, connect the prblock signals to either core logic or I/O pins, excluding the dedicated programming pin, such as DCLK.

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