184.108.40.206. PR Error Recovery Timing Specifications
Timing Diagram: PR Operation with PR_ERROR Triggered - PR Controller Intel FPGA IP (Avalon Streaming), and Timing Diagram: PR Operation with PR_ERROR Triggered - PR Controller Intel FPGA IP (Avalon Memory-Mapped) describe a PR operation that encounters PR_ERROR. When PR_ERROR is triggered, the FPGA SDM operation de-asserts the avst_sink_ready signal to backpressure any remaining corrupted PR bitstream. Next, the error recovery mechanism initiates by re-asserting the avst_sink_ready signal to flush out any remaining corrupted PR bitstream in the Avalon streaming pipeline.
For PR Controller IP designs that have the Avalon memory-mapped interface, when PR_ERROR triggers, continue to write (by asserting both avmm_slave_write and avmm_slave_writedata) until the PR bitstream in the Avalon memory-mapped host depletes, as Timing Diagram: PR Operation with PR_ERROR Triggered - PR Controller Intel FPGA IP (Avalon Memory-Mapped) shows.
The error recovery mechanism continues until you initiate a PR Controller IP reset or another PR operation, as the following illustrations show. Then, you can send a new, uncorrupted PR bitstream to the PR Controller IP.
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