Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
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3.7. Avalon® Streaming Partial Reconfiguration Freeze Bridge IP

The Avalon® Streaming Partial Reconfiguration Freeze Bridge Intel® FPGA IP freezes a PR region Avalon streaming interface when the freeze input signal is high. The Avalon® Streaming Partial Reconfiguration Freeze Bridge IP ensures that any transaction is complete before freezing the connected interface. It is recommended that each Avalon streaming interface to a PR region use an instance of the Freeze Bridge IP.
Figure 75.  Avalon® Streaming Partial Reconfiguration Freeze Bridge
Table 55.   Avalon® Streaming Source Freeze Bridge Interface Behavior
Interface Type Behavior
Source interface in the PR region with packet transfer (old or new persona)
  1. When the freeze signal goes high, the Freeze Bridge handles the startofpacket, endofpacket, and empty bits and does not send transactions to the static region.
  2. When the Freeze Bridge detects a startofpacket transaction without a corresponding endofpacket during the frozen state, this indicates an unfinished transaction.
  3. The bridge then completes the transaction by asserting valid and endofpacket high to the static region for one clock cycle.
  4. The channel signal remains constant, while data bits are set to 'hDEADBEEF and error bit is set to 1’b1.
  5. The illegal_request output signal triggers update of the CSR register in the Partial Reconfiguration Region Controller.
Source interface in the PR region without packet transfer (old or new persona) When the freeze signal is high, the Freeze Bridge does not send transactions to the static region. The Freeze Bridge remains idle until the bridge leaves the frozen state.
Source interface in the PR region with max_channel > 1 (old or new persona) When multiple channels transfer unfinished transactions, the Freeze Bridge tracks the channel values to ensure that all packet transactions from different channels end by asserting the endofpacket bit during the frozen state.
Source interface in the PR region with ready_latency > 0 (old or new persona) When the Freeze Bridge drives endofpacket, valid, or channel outputs to the static region, the Freeze Bridge reads the ready_latency value. The ready_latency value defines the actual clock cycle when the sink component is ready for data.
Figure 76. Source Bridge Handling of Unfinished Packet Transaction During Freeze
Figure 77. PR Freeze Bridge Asserting valid Signal to End Packet Transactions
Table 56.   Avalon® Streaming Sink Freeze Bridge Interface Behavior
Interface Type Behavior
Sink interface in PR region

For transactions that includes packet transfers, when the freeze signal goes high, the Freeze Bridge holds the ready signal high to the static region source until any unfinished transaction completes.

For transactions that do not include packet transfers, when the freeze signal goes high, the Freeze Bridge holds the ready signal low during the freeze period.

The illegal_request signal asserts high to indicate that the current transaction is an error. Configure the design to stop sending transactions to the PR region after the illegal_request signal is high.

Sink interface in PR region with ready_latency > 0 When the Freeze Bridge drives endofpacket, valid, or channel outputs to the PR region, the Freeze Bridge must observe the ready_latency value. The ready_latency value defines the actual clock cycle when the sink component is ready for data.

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