Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.4.2. Ports

The Partial Reconfiguration External Configuration Controller Intel® FPGA IP includes the following interface ports.
Table 34.  Ports
Port Name Width Direction Function
pr_request 1 Input Indicates that the PR process is ready to begin. The signal is a conduit not synchronous to any clock signal.
pr_error 2 Output Indicates a partial reconfiguration error.:
  • 2'b01—general PR error
  • 2'b11—incompatible bitstream error
These signals are conduits not synchronous to any clock source.
pr_done 1 Output Indicates that the PR process is complete. The signal is a conduit not synchronous to any clock signal.
start_addr 1 Input Specifies the start address of PR data in Active Serial Flash. You enable this signal by selecting either Avalon® -ST or Active Serial for the Enable Avalon-ST Pins or Active Serial Pins parameter. The signal is a conduit not synchronous to any clock signal.
reset 1 Input Active high, synchronous reset signal.
out_clock 1 Output Clock source that generates from an internal oscillator.
busy 1 Output

The IP asserts this signal to indicate PR data transfer in progress. You enable this signal by selecting Enable for the Enable busy interface parameter.

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