Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.6.2. Interface Ports

The Avalon® Memory-Mapped Partial Reconfiguration Freeze Bridge IP core has the following interface ports.

Table 50.  Interface Ports

Port

Width

Direction

Description

clock 1 Input Input clock for the IP.
reset_n 1 Input Synchronous reset for the IP.
freeze_conduit_freeze 1 Input When this signal is high, the bridge handles any current transaction properly then freezes the Avalon memory-mapped PR interfaces.
freeze_conduit_illegal_request 1 Output

High on this bus indicates that an illegal request was issued to the bridge during the freeze state.

pr_freeze_pr_freeze 1 Input Enabled freeze port coming from the PR region.
Table 51.   Avalon® Memory-Mapped Agent to PR Region Host Interface Ports

Port

Width

Direction

Description

slv_bridge_to_pr_read 1 Output Optional Avalon® memory-mapped agent bridge to PR region read port.
slv_bridge_to_pr_waitrequest 1 Input Optional Avalon® memory-mapped agent bridge to PR region waitrequest port.
slv_bridge_to_pr_write 1 Output Optional Avalon® memory-mapped agent bridge to PR region write port.
slv_bridge_to_pr_address 32 Output Optional Avalon® memory-mapped agent bridge to PR region address port.
slv_bridge_to_pr_byteenable 4 Output Optional Avalon® memory-mapped agent bridge to PR region byteenable port.
slv_bridge_to_pr_writedata 32 Output Optional Avalon® memory-mapped agent bridge to PR region writedata port.
slv_bridge_to_pr_readdata 32 Input Optional Avalon® memory-mapped agent bridge to PR region readdata port.
slv_bridge_to_pr_burstcount 3 Output Optional Avalon® memory-mapped agent bridge to PR region burstcount port.
slv_bridge_to_pr_readdatavalid 1 Input Optional Avalon® memory-mapped agent bridge to PR region readdatavalid port.
slv_bridge_to_pr_beginbursttransfer 1 Output Optional Avalon® -MM agent bridge to PR region beginbursttransfer port.
slv_bridge_to_pr_debugaccess 1 Output Optional Avalon® memory-mapped agent bridge to PR region debugaccess port.
slv_bridge_to_pr_response 2 Input Optional Avalon® memory-mapped agent bridge to PR region response port.
slv_bridge_to_pr_lock 1 Output Optional Avalon® -MM agent bridge to PR region lock port.
slv_bridge_to_pr_writeresponsevalid 1 Input Optional Avalon® memory-mapped agent bridge to PR region writeresponsevalid port.
Table 52.   Avalon® Memory-Mapped Agent to Static Region Master Interface Ports
Note: Same setting as Avalon® memory-mapped master to PR region agent interface.

Port

Width

Direction

Description

slv_bridge_to_sr_read 1 Input Avalon® memory-mapped agent bridge to static region read port.
slv_bridge_to_sr_waitrequest 1 Output Avalon® memory-mapped agent bridge to static region waitrequest port.
slv_bridge_to_sr_write 1 Input Avalon® memory-mapped agent bridge to static region write port.
slv_bridge_to_sr_address 32 Input Avalon® memory-mapped agent bridge to static region address port.
slv_bridge_to_sr_byteenable 4 Input Avalon® memory-mapped agent bridge to static region byteenable port.
slv_bridge_to_sr_writedata 32 Input Avalon® memory-mapped agent bridge to static region writedata port.
slv_bridge_to_sr_readdata 32 Output Avalon® memory-mapped agent bridge to static region readdata port.
slv_bridge_to_sr_burstcount 3 Input Avalon® memory-mapped agent bridge to static region burstcount port.
slv_bridge_to_sr_beginbursttransfer 1 Input Avalon® memory-mapped agent bridge to static region beginbursttransfer port.
slv_bridge_to_sr_debugaccess 1 Input Avalon® -MM agent bridge to static region debugaccess port.
slv_bridge_to_sr_response 2 Output Avalon® memory-mapped agent bridge to static region response port.
slv_bridge_to_sr_lock 1 Input Avalon® memory-mapped agent bridge to static region lock port.
slv_bridge_to_sr_writeresponsevalid 1 Output Avalon® memory-mapped agent bridge to static region writereponsevalid port.
Table 53.   Avalon® Memory-Mapped Master to PR Region Agent Interface Ports

Port

Width

Direction

Description

mst_bridge_to_pr_read 1 Input Optional Avalon® memory-mapped master bridge to PR region read port.
mst_bridge_to_pr_waitrequest 1 Output Optional Avalon® memory-mapped master bridge to PR region waitrequest port.
mst_bridge_to_pr_write 1 Input Optional Avalon® memory-mapped master bridge to PR region write port.
mst_bridge_to_pr_address 32 Input Optional Avalon® memory-mapped master bridge to PR region address port.
mst_bridge_to_pr_byteenable 4 Input Optional Avalon® -MM master bridge to PR region byteenable port.
mst_bridge_to_pr_writedata 32 Input Optional Avalon® -MM master bridge to PR region writedata port.
mst_bridge_to_pr_readdata 32 Output Optional Avalon® memory-mapped master bridge to PR region readdata port.
mst_bridge_to_pr_burstcount 3 Input Optional Avalon® memory-mapped master bridge to PR region burstcount port.
mst_bridge_to_pr_readdatavalid 1 Output Optional Avalon® memory-mapped master bridge to PR region readdatavalid port.
mst_bridge_to_pr_beginbursttransfer 1 Input Optional Avalon® memory-mapped master bridge to PR region beginbursttransfer port.
mst_bridge_to_pr_debugaccess 1 Input Optional Avalon® memory-mapped master bridge to PR region debugaccess port.
mst_bridge_to_pr_response 2 Output Optional Avalon® memory-mapped master bridge to PR region response port.
mst_bridge_to_pr_lock 1 Input Optional Avalon® memory-mapped master bridge to PR region lock port.
mst_bridge_to_pr_writeresponsevalid 1 Output Optional Avalon® memory-mapped master bridge to PR region writeresponsevalid port.
Table 54.   Avalon® Memory-Mapped Master to Static Region Agent Interface PortsSame setting as Avalon® Memory-Mapped agent to PR region master interface.

Port

Width

Direction

Description

mst_bridge_to_sr_read 1 Output Avalon® memory-mapped master bridge to static region read port.
mst_bridge_to_sr_waitrequest 1 Input Avalon® memory-mapped bridge to static region waitrequest port.
mst_bridge_to_sr_write 1 Output Avalon® memory-mapped master bridge to static region write port.
mst_bridge_to_sr_address 32 Output Avalon® memory-mapped master bridge to static region address port.
mst_bridge_to_sr_byteenable 4 Output Avalon® memory-mapped master bridge to static region byteenable port.
mst_bridge_to_sr_writedata 32 Output Avalon® memory-mapped master bridge to static region writedata port.
mst_bridge_to_sr_readdata 32 Input Avalon® memory-mapped master bridge to static region readdata port.
mst_bridge_to_sr_burstcount 3 Output Avalon® memory-mapped master bridge to static region burstcount port.
mst_bridge_to_sr_readdatavalid 1 Input Avalon® memory-mapped master bridge to static region readdatavalid port.
mst_bridge_to_sr_beginbursttransfer 1 Output Avalon® memory-mapped master bridge to static region beginbursttransfer port.
mst_bridge_to_sr_debugaccess 1 Output Avalon® memory-mapped master bridge to static region debugaccess port.
mst_bridge_to_sr_response 2 Input Avalon® memory-mapped master bridge to static region response port.
mst_bridge_to_sr_lock 1 Output Avalon® memory-mapped master bridge to static region lock port.
mst_bridge_to_sr_writeresponsevalid 1 Input Avalon® memory-mapped master bridge to static region writeresponsevalid port.
Figure 73.  Avalon® Memory-Mapped Host Interface Ports
Figure 74.  Avalon® Memory-Mapped Agent Interface Ports

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