Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

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ID 683834
Date 1/11/2022
Public

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2.11.1. Debugging PR Designs with the Signal Tap Logic Analyzer

To use the Signal Tap logic analyzer to debug PR designs, you must create a debug bridge to extend Signal Tap debugging into the PR partition. You can then use Signal Tap to debug by connecting to the debug bridge. To use the debug bridge, you instantiate the SLD JTAG Bridge Agent Intel® FPGA IP, SLD JTAG Bridge Host Intel® FPGA IP, and Intel Configuration Reset Release Endpoint to Debug Logic IP for each PR region in your design.

You must instantiate the following IP in your design to ensure you can use Signal Tap to debug your static as well as PR region:

  1. Instantiate the SLD JTAG Bridge Agent IP in the static region.
  2. Instantiate the SLD JTAG Bridge Host IP and the Intel Configuration Reset Release Endpoint to Debug Logic IP in the PR region of the default persona.
  3. Instantiate the SLD JTAG Bridge Host IP and the Intel Configuration Reset Release Endpoint to Debug Logic IP, for each of the personas, whenever creating revisions for the personas.

The Signal Tap logic analyzer uses the hierarchical debug capabilities provided by the Intel® Quartus® Prime software to tap signals in the static and PR regions simultaneously.

You can debug multiple personas present in your PR region, as well as multiple PR regions. For complete information on the debug infrastructure using hierarchical hubs, refer to Intel Quartus Prime Pro Edition User Guide: Debug Tools.

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