Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022

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2.7.1. Partial Reconfiguration Design Guidelines

The following table lists important design guidelines at various steps in the PR design flow:

Table 6.  Partial Reconfiguration Design Guidelines
PR Design Step Guideline Reason

Designing for partial reconfiguration

Do not assume initial states in registers inside PR region. After PR is complete, ensure that you reset all the control path registers to a known state, but omit the data path registers.

Registers inside the PR region contain undefined values after reconfiguration. Omitting data path registers reduces congestion on reset signals.

You cannot define synchronous reset as a global signal for Intel® Arria® 10 or Intel® Cyclone® 10 GX partial reconfiguration.

PR regions do not support synchronous reset of registers as a global signal, because the Intel® Arria® 10 and Intel® Cyclone® 10 GX LAB does not support synchronous clear (sclr) signal on a global buffer. The LAB supports the asynchronous clear (aclr) signal driven from a local input, or from a global network row clock. As a result, only the aclr can be a global signal, feeding registers in a PR region.

The PRESERVE_FANOUT_FREE_NODE assignment cannot preserve a fanout-free register that has no fanout inside the Verilog HDL or VHDL module in which you define it. To preserve these fanout-free registers, implement the noprune pragma in the source file:

(*noprune*)reg r;

If there are multiple instances of this module, with only some instances requiring preservation of the fanout-free register, set a dummy pragma on the register in the HDL and also set the PRESERVE_FANOUT_FREE_NODE assignment. This dummy pragma allows the register synthesis to implement the assignment. For example, set the following dummy pragma for a register r in Verilog HDL:

(*dummy*)reg r;

Then set this instance assignment:

set_instance_assignment -name \
    -to r;
The PRESERVE_FANOUT_FREE_NODE assignment does not apply when a register is not used in the Verilog HDL or VHDL module in which it is defined.

Partitioning the design

Register all the inputs and outputs for your PR region.

Improves timing closure and time budgeting.

Reduce the number of signals interfacing the PR region with the static region in your design.

Reduces the wire LUT count.

Create a wrapper for your PR region.

The wrapper creates a common footprint to the static region.

Drive all the PR region output ports to inactive state when the PR region is held in reset and the freeze bit is asserted for the PR region.

Prevents the static region logic from receiving random data during the partial reconfiguration operation.

PR boundary I/O interface must be a superset of all the PR persona I/O interfaces.

Ensures that each PR partition implements the same ports.

Preparing for partial reconfiguration

Complete all pending transactions.

Ensures that the static region is not in a wait state.

Maintaining a partially working system during partial reconfiguration

Hold all outputs to known constant values.

Ensures that the undefined values the PR region receives during and after the reconfiguration do not affect the PR control logic.

Initializing after partial reconfiguration

Initialize after reset.

Retrieves state from memory or other device resources.

Debugging the design using Signal Tap Logic Analyzer

Store all the tapped signals from a persona in one .stp file.

The current version of the Intel® Quartus® Prime software supports only one .stp (Signal Tap file) per revision. This limitation requires you to select partitions, one at a time, to tap.

Do not tap across regions in the same .stp file.

Ensures consistent interface (boundary) across all personas.

Tap only the pre-synthesis signals. In the Node Finder, filter for Signal Tap: pre-synthesis.

Ensures that the signal tapping of PR personas start from synthesis.

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