Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.2.3. Ports

The Partial Reconfiguration Controller Intel® FPGA IP includes the following interface ports.
Figure 40.  Avalon® Streaming Sink Interface Ports
Figure 41.  Avalon® Memory-Mapped Agent Interface Ports
5
Table 14.  Clock/Reset Ports
Port Name Width Direction Function

reset

1

Input

Asynchronous reset for the PR Controller IP core. Resetting the PR Controller IP core during a partial reconfiguration operation can cause the device to lock up.

clk

1

Input

Input clock to the PR Controller IP core.

The input clock must be free-running. The IP core has a maximum clock frequency of 200 MHz.

Table 15.   Avalon® Streaming Sink interface PortsThese ports are available when you enable the Avalon® Streaming sink interface.
Port Name Width Direction Function

pr_start

1

Input

A signal arriving at this port asserted high initiates a PR event. You must assert this signal high for a minimum of one clock cycle, and de-assert it low, prior to the end of the PR operation.

avst_sink_data[]

32|64

Input

Avalon® streaming data signal that is synchronous with the rising edge of the clk signal. The Input data width parameter specifies this port width.

avst_sink_valid

1

Input

Avalon® streaming data valid signal that indicates the avst_sink_data port contains valid data.

avst_sink_ready

1

Output

Avalon® streaming ready signal that indicates the device is ready to read the streaming data on the avst_sink_data port whenever the avst_sink_valid signal asserts high. Stop sending valid data when this port is low.

status[2:0]

3

Output

A 3-bit error output that indicates the status of a PR event. Once the outputs latch high as follow, you can only reset the outputs at the beginning of the next PR event:

3’b000 – power-up nreset asserted

3’b001 – configuration system is busy

3’b010 – PR operation is in progress

3’b011 – PR operation successful

3’b100 – PR_ERROR is triggered

3’b101 – Reserved

3'b110 – Incompatible bitstream error

3'b111 – Reserved

protocol_error 1 Output Reads out the error bit from the CSR register.
pr_fw_handshake 8 Output Indicates the current state of the mailbox handshake between the PR IP and the SDM firmware in the PR operation.
pr_fw_response 32 Output SDM firmware mailbox response.
Table 16.   Avalon® Memory-Mapped Agent Interface PortsThese ports are available when you enable the Avalon® memory-mapped agent interface.
Port Name Width Direction Function

avmm_slave_address

4

Input

Avalon® memory-mapped address bus in the unit of Word addressing.

avmm_slave_read

1

Input

Avalon® memory-mapped read control.

avmm_slave_readdata

32

Output

Avalon® memory-mapped read data bus.

avmm_slave_write

1

Input

Avalon® memory-mapped write control.

avmm_slave_writedata

32

Input

Avalon® memory-mapped write data bus.

avmm_slave_waitrequest

1

Output

Upon assertion, indicates that the IP is busy and the IP is unable to respond to a read or write request.

irq

1

Output

Interrupt signal when you enable the Enable interrupt interface parameter.
5 The terms host and agent now replace non-inclusive terms in the Avalon® Memory Mapped specification.

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