Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.3.2. Reconfiguration Sequence

Partial reconfiguration occurs through the Avalon® memory-mapped agent interface in the following sequence:
  1. Avalon® memory-mapped host component writes 0x01 to IP address offset 0x1 to trigger PR operation.
  2. Optionally poll the status register until PR Operation in Progress. Not polling results in waitrequest on first word.
  3. Avalon® memory-mapped host component writes PR bitstream to IP address offset 0x0, until all the PR bitstream writes complete. When enhanced decompression is on, waitrequest activates throughout the PR operation. Ensure that your host can handle waitrequest from the agent interface.
  4. Avalon® memory-mapped host component reads the data from IP address offset 0x1 to check the status[2:0] value. Optionally, the Avalon® memory-mapped host component reads the status[2:0] of this IP during a PR operation to detect any early failure, for example, PR_ERROR.

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