Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration

ID 683834
Date 1/11/2022
Public

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3.2.6.1. SDM Firmware Error Reporting Timing Specification

Timing Diagram: PR Operation with SDM Firmware Error Reporting Signals - PR Controller Intel FPGA IP (Avalon Streaming) shows the timing diagram of PR operation with the SDM firmware error reporting signal usage in Avalon-ST mode of the PR Controller IP. During PR operation, you can read the pr_fw_handshake and pr_fw_response signals after a PR error to learn more about the error. For example, once you detect the PR operation has ended with the status[2:0], you can continue by reading the pr_fw_handshake and pr_fw_response signals.

In this example, the PR operation ends with PR_ERROR, as indicated by the status[2:0] = 3’b100. For error details, you can read the pr_fw_handshake to determine in which stage the PR operation fails. You can read pr_fw_response to determine the error code that the SDM returns.

Figure 51. Timing Diagram: PR Operation with SDM Firmware Error Reporting Signals - PR Controller Intel FPGA IP (Avalon Streaming)

The following steps correspond to the sequence in the timing diagram:

  1. Assert pr_start to begin the PR operation.
  2. Stream the PR bitstream on avst_sink_ready and avst_sink_valid ports.
  3. The SDM detects a PR_ERROR causing avst_sink_ready to be de-asserted to backpressure incoming PR bitstream.
  4. You detect that status[2:0] is updated to 0x4 (3’b100) to indicate that ‘PR_ERROR is triggered’. From this status information, you can determine that an error occurred during the PR operation.
  5. To learn more about the PR operation failure, read the pr_fw_handshake[7:0] and pr_fw_response[31:0] signals to determine the error code and PR stage of the failure.

Timing Diagram: PR Operation with SDM Firmware Error Reporting Signals - PR Controller Intel FPGA IP (Avalon Memory-Mapped) shows the PR operation timing diagram with the SDM firmware error reporting signal usage in Avalon memory-mapped mode of the PR Controller Intel FPGA IP. During a PR operation, you can read the CSR registers (0x3 for PR_FW_HANDSHAKE, and 0x4 for PR_FW_RESPONSE) after a PR error to learn more about the error. For example, once you detect that the PR operation ends with an error by IRQ assertion, and after reading CSR register 0x1 (PR_CSR) that holds the PR status[2:0] value, you can continue by reading the CSR registers 0x3 and 0x4, as .

Figure 52. Timing Diagram: PR Operation with SDM Firmware Error Reporting Signals - PR Controller Intel FPGA IP (Avalon Memory-Mapped)

The following steps correspond to the sequence in the timing diagram:

  1. Start the PR operation by writing to CSR address 0x1 (PR_CSR) with 0x21.This action enables the use of the irq signal and sets the pr_start to begin the PR operation. After 1 clock cycle, status[2:0] updates to 0x2 (3’b010) to indicate ‘PR operation is in progress'.
  2. Read the CSR address 0x1 (PR_CSR) to obtain the status[2:0] of the PR operation. The value read back is 0x24, which translates to status[2:0] = 3’b010, indicating 'PR operation is in progress'.
  3. Start writing the PR bitstream in CSR address 0x0 (PR_DATA).
  4. You read PR_CSR and observe that irq was asserted and that PR_ERROR is the status.

The pr_fw_handshake register holds the current location of the mailbox handshake between the PR IP and the SDM. If the PR IP is interrupted during PR, the pr_fw_handshake register indicates the last position of the mailbox handshake. The pr_fw_handshake register also enables you to associate the value held in pr_fw_response to a specific mailbox command.

Table 17.  pr_fw_handshake Register Values
Register Value Description
0 The PR IP has not yet sent any mailbox command to the SDM to initiate the partial reconfiguration operation.
1 The PR IP has sent the mailbox command to the SDM to initiate the partial reconfiguration operation and is awaiting a response.
2 PR IP has received the mailbox response from the SDM on the partial reconfiguration operation initiation.
3 The PR IP has sent the mailbox command to the SDM to query the last partial reconfiguration status and is awaiting a response.
4 The PR IP has received the mailbox response from the SDM on the last partial reconfiguration status.
5 The PR IP has sent the mailbox command to the SDM to initiate the partial reconfiguration operation from the data source selected by MSEL and is awaiting a response.
6 The PR IP has received the mailbox response from the SDM on the partial reconfiguration operation from the data source selected by MSEL.
7 Reserved.

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